参数资料
型号: MAX8655ETN+T
厂商: Maxim Integrated Products
文件页数: 9/23页
文件大小: 0K
描述: IC REG BUCK ADJ 25A 56TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.7 V ~ 5.5 V
输入电压: 4.5 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 1MHz
电流 - 输出: 25A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 56-TQFN-EP(8x8)
Highly Integrated, 25A, Wide-Input,
Internal MOSFET, Step-Down Regulator
Pin Description (continued)
PIN
40
41
43
44
45
46
47
50
NAME
ILIM2
SCOMP
POK
FSYNC
MODE
SYNCO
BST
LXB
GND-EP
PVIN-EP
LX-EP
FUNCTION
Programmable Current-Limit Input. Connect a resistor from ILIM2 to GND to set the valley current
limit. See the Setting the Current Limit section.
Programmable Slope-Compensation Input. Internal slope-compensation voltage rate is the voltage at
SCOMP times 0.1 divided by the oscillator period (T). Connect SCOMP to AVL or GND to set to the
default of 250mV/T or 125mV/T, respectively.
Open-Drain Power-OK Output. POK goes high impedance when the output voltage rises above 91%
of the nominal regulation voltage. POK pulls low during shutdown or when the output drops below
88% of the nominal regulation voltage.
Frequency Set and Synchronization Input. Connect a resistor from FSYNC to GND to set the switching
frequency, or drive with a clock signal to synchronize between 160kHz and 1.2MHz. See the
Switching Frequency and Synchronization section.
Current-Limit Operating Mode Selection. Connect MODE to AVL for latch-off current limit or connect
MODE to GND for automatic recovery current limit.
Synchronization Output. Provides a clock output for synchronizing another MAX8655 with 180°
out-of-phase operation.
Boost Capacitor Connection. Connect a 0.22μF ceramic capacitor from BST to LXB.
LX Boost Capacitor Connection. Connect a 0.22μF ceramic capacitor between LXB and BST.
Exposed Pad. Connect to GND externally. See the Pin Configuration .
Exposed Pad. Internally connected to PVIN. See the Pin Configuration .
Exposed Pad. Internally connected to LX. See the Pin Configuration .
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