参数资料
型号: MAX8744AETJ+T
厂商: Maxim Integrated Products
文件页数: 13/36页
文件大小: 0K
描述: IC CNTRLR PWR SUP QUAD 32TQFN
标准包装: 2,500
应用: 控制器,笔记本电脑电源系统
输入电压: 6 V ~ 26 V
输出数: 4
输出电压: 3.3V,5V,1 V ~ 26 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME
ONA
DRVA
ILIM
SHDN
ON3
ON5
REF
GND
FSEL
SKIP
FB5
CSH5
CSL5
PGOOD5
FUNCTION
Auxiliary LDO Enable Input. When ONA is pulled low, OUTA is high impedance and the secondary
feedback control is disabled. When ONA is driven high, the controller enables the auxiliary LDO.
Auxiliary LDO Transistor Base Driver. Connect DRVA to the base of a pnp power transistor. Add a
680 Ω pullup resistor between the base and emitter.
Peak Current-Limit Threshold Adjustment. The current-limit threshold defaults to 50mV if ILIM is pulled
up to LDO5. In adjustable mode, the current-limit threshold across CSH_ and CSL_ is precisely 1/10
the voltage seen at ILIM over a 0.5V to 2.0V range. The logic threshold for switchover to the 50mV
default value is approximately V LDO5 - 1V.
Shutdown Control Input. The device enters its 8μA supply-current shutdown mode if V SHDN is less
than the SHDN input falling edge trip level and does not restart until V SHDN is greater than the SHDN
input rising-edge trip level. Connect SHDN to V IN for automatic startup. SHDN can be connected to
V IN through a resistive voltage-divider to implement a programmable undervoltage lockout.
3.3V SMPS Enable Input. Driving ON3 high enables the 3.3V SMPS, while pulling ON3 low disables
the 3.3V SMPS. If ON3 is connected to REF, the 3.3V SMPS starts after the 5V SMPS reaches
regulation (delayed start). Drive ON3 below the clear fault level to reset the fault latch.
5V SMPS Enable Input. Driving ON5 high enables the 5V SMPS, while pulling ON5 low disables the
5V SMPS. If ON5 is connected to REF, the 5V SMPS starts after the 3.3V SMPS reaches regulation
(delayed start). Drive ON5 below the clear fault level to reset the fault latch.
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1μF or greater ceramic
capacitor. The reference sources up to 50μA for external loads. Loading REF degrades output-
voltage accuracy according to the REF load-regulation error. The reference shuts down when the
system pulls SHDN low.
Analog Ground. Connect the exposed backside pad to GND.
Frequency Select Input. This three-level logic input sets the controllers’ switching frequency. Connect
to LDO5, REF, or GND to select the following typical switching frequencies:
LDO5 = 500kHz, REF = 300kHz, GND = 200kHz.
Pulse-Skipping Control Input. Connect to LDO5 for low-noise, forced-PWM operation. Connect to REF
for automatic, low-noise, pulse-skipping operation at light loads. Connect to GND for automatic, high-
efficiency, pulse-skipping operation at light loads.
Feedback Input for the 5V SMPS. Connect to LDO5 for the preset 5V output. In adjustable mode, FB5
regulates to 2V.
Positive Current-Sense Input for the 5V SMPS. Connect to the positive terminal of the current-sense
element. Figure 7 describes two different current-sensing options—using accurate sense resistors or
lossless inductor DCR sensing.
Output-Sense and Negative Current-Sense Input for the 5V SMPS. When using the internal preset 5V
feedback-divider (FB5 = LDO5), the controller uses CSL5 to sense the output voltage. Connect to the
negative terminal of the current-sense element. CSL5 also serves as the bootstrap input for LDO5.
Open-Drain, Power-Good Output for the 5V SMPS. PGOOD5 is pulled low if CSL5 drops more than
10% (typ) below the normal regulation point. PGOOD5 is held low during soft-start and shutdown.
PGOOD5 becomes high impedance when CSL5 is in regulation.
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