参数资料
型号: MAX8751ETJ+T
厂商: Maxim Integrated
文件页数: 10/27页
文件大小: 0K
描述: IC CNTRLR CCFL INV 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: CCFL 控制器
频率: 30 ~ 80 kHz
电流 - 电源: 3.2mA
电源电压: 6 V ~ 28 V
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
Fixed-Frequency, Full-Bridge CCFL
Inverter Controller
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NAME
VFB
TFLT
CNTL
SHDN
LSYNC
LFCK
DPWM
PSCK
HFCK
HSYNC
SEL
LF
HF
PS1
PGND2
GL2
BST2
FUNCTION
Transformer Secondary Voltage-Feedback Input. VFB pin sets secondary overvoltage limit by using a
capacitive voltage-divider between the high voltage of the CCFL lamp and GND. When the peak
voltage on VFB exceeds the internal overvoltage threshold, the controller turns on an internal current
sink, discharging the COMP capacitor, limiting the secondary voltage. See the Transformer
Secondary Voltage Limiting section for details.
Fault Timer-Adjustment Pin. A fault condition sets an internal current source to charge a capacitor
connected between TFLT and GND. Connect a capacitor from TFLT to GND to set the timeout period
for open-lamp fault and secondary short-circuit faults. See the Lamp-Out Protection section for
details.
Brightness Control Input. The usable brightness control range is from 0 to 2V. V CNTL = 0 represents
minimum brightness (10% DPWM duty cycle), V CNTL = 2V represents full brightness (100% DPWM
duty cycle). When V CNTL is between 2V and 3V, the brightness is still 100%. The MAX8751 enters into
slave mode when CNTL is connected to V CC . See the DPWM Dimming Control section for details.
Shutdown Control Input. The MAX8751 shuts down when SHDN is pulled to GND.
DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When
SEL is connected to V CC , the duty cycle of the LSYNC signal determines the brightness.
Internal DPWM Oscillator Clock Output. LFCK becomes a logic-level input when CNTL is connected
to V CC .
DPWM Signal Output. The DPWM output is used to control the DPWM frequency of the slave IC in
master-slave operation. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) section for details.
Phase-Shift Clock Output. See the Slave Operation (HFCK, LFCK, PSCK, DPWM) and Phase Shift
(PS1, PS2) sections for details.
Main Switching Oscillator Clock Output. HFCK is a logic-level input when CNTL is connected to V CC .
Main Switching Frequency Sync Input. Switching frequency can be synchronized with an external
signal on HSYNC.
Brightness Control Select Input. Brightness can be adjusted with an analog voltage on CNTL or with
an external sync signal. Connecting SEL to V CC enables analog control input. Connect SEL to V CC to
enable brightness control using external sync signal.
Frequency Adjustment Pin for Internal DPWM Oscillator. Connect a resistor from LF to GND to set the
internal DPWM oscillator frequency. f DPWM = 208Hz × 150k ? / R LF . LF becomes a logic-level input
when CNTL is connected to V CC . See the DPWM Dimming Control section for details.
Frequency Adjustment Pin for Main Switching Oscillator. Connect a resistor from HF to GND to set the
main oscillator frequency. f SW = 54kHz × 100k ? / R HF . HF is a logic-level input when CNTL is
connected to V CC .
Phase-Shift Select Input for Slave. For details, see the Slave Operation (HFCK, LFCK, PSCK, DPWM)
section.
Power Ground. PGND is the return for the GL2 gate driver.
Gate-Driver Output for Low-Side MOSFET NL2
High-Side Gate Driver GH2 Supply Input. The MAX8751 includes an integrated boost diode. Connect
a 0.1μF capacitor between LX2 and BST2 to complete the bootstrap circuit.
10
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