参数资料
型号: MAX8751ETJ+T
厂商: Maxim Integrated
文件页数: 18/27页
文件大小: 0K
描述: IC CNTRLR CCFL INV 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: CCFL 控制器
频率: 30 ~ 80 kHz
电流 - 电源: 3.2mA
电源电压: 6 V ~ 28 V
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
Fixed-Frequency, Full-Bridge CCFL
Inverter Controller
Secondary Current Limit (ISEC)
The secondary current limit provides fail-safe protection
in case of short circuit or leakage from the high-voltage
terminal to ground. ISEC monitors the voltage across a
sense resistor placed between the transformer’s low-
voltage secondary terminal and ground. The ISEC volt-
age is continuously compared to the ISEC regulation
threshold (1.22V, typ). Any time the ISEC voltage
exceeds the threshold, a controlled current is drawn
from COMP to reduce the on-time of the bridge’s high-
side switches. At the same time, the MAX8751 charges
the TFLT capacitor with a 126μA current. The MAX8751
latches off when the voltage on TFLT exceeds 4V.
Unlike the normal shutdown mode, the linear regulator
output (V CC ) remains at 5.35V. Toggling SHDN or
cycling the input power reactivates the device.
Slave Operation (HFCK, LFCK,
PSCK, DPWM)
The MAX8751 supports master-slave operation. Up to
five MAX8751s can be connected in a daisy-chain con-
figuration as shown in Figure 6. The same device can
be used either as a master IC or as a slave IC. Each
MAX8751 is the master of the next IC in the chain and
at the same time, it is also the slave of the previous IC
in the chain.
Connecting CNTL to V CC enables the slave mode. In
the slave mode, the switching frequency and DPWM
frequency are synchronized with the previous
MAX8751 in the chain. To synchronize the switching
frequency, connect the HFCK pins of the slave IC and
master IC together, and connect the PSCK pin of the
DIMMING
CNTL
HF
master IC to the HF pin of the slave IC. To synchronize
ON/OFF
SHDN
HFCK
LFCK
MASTER
LF
PSCK
DPWM
the DPWM frequency, connect the LFCK pins of the
slave IC and master IC together, and connect the
DPWM pin of the master IC to the LF pin of the slave IC.
The CNTL brightness control is disabled in the slave
mode. The master directly controls the brightness set-
ting of the slave by connecting the DPWM pin of master
VCC
CNTL
SHDN
HF
LF
to LF pin of slave.
Phase Shift (PS1, PS2)
HFCK
LFCK
SLAVE 1
PSCK
DPWM
The MAX8751 provides phase shift for both the DPWM
operation and switching of MOSFETS when connected
in a daisy-chain configuration. This phase shift reduces
input ripple current, hence significantly reducing input
RMS current. This reduction of input RMS current
CNTL
SHDN
HF
LF
reduces the input capacitor requirement, hence the
size of capacitor. The phase shift can be programmed
HFCK
LFCK
SLAVE 2
PSCK
DPWM
using two logic input pins (PS1 and PS2). These two
pins combined together give four choices of phase
shift: 72°, 90°, 120°, and 180°. The selection of the
phase shift is based on the number of MAX8751s used
in the daisy-chain. Use the following equation to deter-
mine the appropriate phase shift:
Phase shift = 360° / number of phases
CNTL
HF
Table 1 gives the suggested selection of phase shift for
SHDN
HFCK
LFCK
SLAVE N
LF
PSCK
DPWM
different number of phases. All master and slave ICs
should use the same setting for PS1 and PS2.
Table 2 summarizes the MAX8751’s operation in all
modes.
Figure 6. Master-Slave Operation
18
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