参数资料
型号: MAX8810AETM+
厂商: Maxim Integrated Products
文件页数: 25/50页
文件大小: 0K
描述: IC CNTRLR PWM W/MOSFET 48TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: 控制器,Intel VR10、VR11
输入电压: 4.5 V ~ 5.5 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
VRD11/VRD10, K8 Rev F 2/3/4-Phase PWM
Controllers with Integrated Dual MOSFET Drivers
low. Once V VL_ is above the UVLO threshold and EN is
low, DL_ is kept high and DH_ is kept low. This pre-
vents the output from rising before a valid EN signal
is given.
monitor an active-high, open-drain VRHOT output.
Connect a resistor from VRTSET to GND to set the tem-
perature-monitoring threshold. The resistor is calculat-
ed as follows:
Boost Circuit for High-Side MOSFET Driver
The gate-drive voltage for the high-side MOSFET dri-
vers is generated by a flying-capacitor boost circuit.
R VRTSET =
800
0 . 6 K T
in k Ω
The capacitor between BST_ and LX_ is charged from
the VL_ supply through an internal switch while the low-
side MOSFET is on. When the low-side MOSFET is
switched off, the stored voltage on the capacitor is
stacked above LX_ to provide the necessary turn-on
voltage for the high-side MOSFET(s). No external boost
diode is needed. See the Boost Capacitor Selection
section for details on selecting the correct capacitor.
Thermal Protection
The MAX8809A/MAX8810A feature a thermal-fault-pro-
tection circuit. When the junction temperature rises
above +160 ° C typical, an internal thermal sensor acti-
vates the shutdown circuit to hold all MOSFET drivers
and active PWM outputs low to disable switching. The
thermal sensor reactivates the controller after the junc-
tion temperature cools by 25 ° C typical.
Temperature Monitoring (VRTSET, VRHOT)
The MAX8809A/MAX8810A contain temperature-moni-
toring circuitry that allows the user to program a tem-
perature trip point between +60 ° C and +125 ° C, and
Table 3. Temperature Scale Factor
where K T is a temperature scale factor specifically for
the Panasonic ERTJ1VR103 NTC thermistor. Table 3
provides values of K T and the closest standard 1%
R VRTSET values needed to program the VRHOT thresh-
old over a +60 ° C to +125 ° C range. R VRTSET must be
greater than 20k Ω . Contact your local Maxim represen-
tative for information on using other thermistors.
Architecture Selection and Timing
AMD K8 Rev F
The AMD K8 Rev F processor uses a 6-bit VID code
that specifies a 0.375V to 1.55V output voltage range
(see Table 4). Leave SEL unconnected to select the
AMD K8 Rev F architecture. The startup sequencing
and timing specifications are shown in Figure 10. Note
that the VID input defines the AMD processor boot
level, and there is no internal default. The boot level is
not latched; therefore, if the codes change during soft-
start, the boot level also changes.
Extended Intel VRD10
The Intel VRD10 processor uses a 7-bit VID code that
specifies a 0.83125V to 1.6V output voltage range (see
Table 5). Connect SEL to GND to select the VRD10
TEMPERATURE ( ° C)
+60
+65
+70
+75
+80
+85
+90
+95
+100
+105
+110
+115
+120
+125
K T
4.497
5.453
6.580
7.903
9.447
11.244
13.325
15.725
18.484
21.643
25.247
29.345
33.988
39.231
R VRTSET (k Ω )
294
243
200
169
140
118
100
84.5
71.5
61.9
52.3
45.3
39.2
34
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
Intel VRD11
The Intel VRD11 processor uses an 8-bit VID code that
specifies a 0.3125V to 1.6V output voltage range (see
Table 6). Connect SEL to V CC to select the VRD11
architecture. The startup sequencing and timing speci-
fications are shown in Figure 9. The Intel boot level is
internally set to 1.1V; therefore, the VID inputs are
ignored during soft-start. In compliance with the Intel
VRD specifications, there is a typical 2.2ms delay after
EN is asserted before soft-start begins. This delay is
not included in the soft-start time set by SS/OVP.
______________________________________________________________________________________
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