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参数资料
| 型号： | MAX8819CETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/29页 |
| 文件大小： | 0K |
| 描述： | IC PMIC W/INT CHARGER 28TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 手持/移动设备 |
| 电源电压： | 4.1 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
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PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V EP = V GND = 0V, V BAT = 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V FB1 = V FB2 = V FB3 = 1.1V, V FB4 = 0.6V,
PV13 = PV2 = SYS, T A = -40°C to +85°C, capacitors as shown in Figure 1, R CISET = 3k Ω , unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LED DIMMING CONTROL (EN4)
EN4 Low Shutdown Delay
EN4 High Enable Delay (Figure 8)
EN4 Low Time
EN4 High Time
t SHDN
t HI_INIT
t LO
t HI
100
0.5
0.5
2
3.2
500
ms
μs
μs
μs
RESET ( RST1 )
Reset Trip Threshold
Reset Deassert Delay Time
V THRST
t DRST
Voltage from FB1 to GND, V FB1 falling,
50mV hysteresis
0.765
180
0.858
200
0.945
220
V
ms
Reset Glitch Filter
t GLRST
50
μs
LOGIC (DLIM1, DLIM2, EN123, EN4, CHG , RST 1 )
Logic Input-Voltage Low
Logic Input-Voltage High
V DC = 4.1V to 5.5V, V SYS = 2.6V to 5.5V
V DC = 4.1V to 5.5V, V SYS = 2.6V to 5.5V
1.2
0.4
V
V
Logic Input Pulldown Resistance
Logic Leakage Current
Logic Output Voltage Low
Logic Output-High Leakage
Current
V LOGIC = 0.4V to 5.5V, CEN, EN123, EN4
V LOGIC = 0 to 5.5V, DLIM1, DLIM2
I SINK = 1mA
V LOGIC = 5.5V
400
-1.0
-1.0
760
+0.001
7
+0.001
1200
+1.0
15
+1.0
k
μA
mV
μA
Note 3: Limits are 100% production tested at T A = +25°C. Limits over the operating temperature range are guaranteed through cor-
relation using statistical quality control (SQC) methods.
Note 4: The charger transitions from done to fast-charge mode at this BAT recharge threshold.
Note 5: The charger transitions from fast-charge to top-off mode at this top-off threshold (Figure 2).
Note 6: The maximum output current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance,
n-channel on-resistance, oscillator frequency, input voltage range, and output voltage range. The parameter is stated for
a 4.7μH inductor with 0.13 Ω series resistance. See the Step-Down Converter Maximum Output Current section for more
information.
Note 7: The step-down output voltages are 1% high with no load due to the load-line architecture.
Note 8: The skip-mode current threshold is the transition point between fixed-frequency PWM operation and skip-mode operation.
The specification is given in terms of output load current for inductor values shown in the typical application circuit (Figure 1).
Note 9: Line regulation for the step-down converters is measured as Δ V OUT / Δ D, where D is the duty cycle (approximately
V OUT /V IN ).
Note 10: REG2 is disabled by connecting PV2 to ground, decreasing the quiescent current.
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