参数资料
型号: MAX8900DEWV+T
厂商: Maxim Integrated Products
文件页数: 32/35页
文件大小: 0K
描述: IC LI BATTERY CHARGER 1.2A WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 锂离子(Li-Ion)、锂聚合物(Li-Pol)
电源电压: 3.4 V ~ 6.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 30-WFBGA,WLBGA
供应商设备封装: 30-WLP
包装: 带卷 (TR)
MAX8900A/MAX8900B/MAX8900C
1.2A Switch-Mode Li+ Chargers with ±22V Input
Rating and JEITA Battery Temperature Monitoring
The guidelines at the top are the most critical:
1) When the step-down converter’s high-side MOSFET
turns on, C INBP delivers a high di/dt current pulse to
INBP. Because of this high di/dt current pulse, place
C INBP close to INBP to minimize the parasitic imped-
ance in the PCB trace.
2) When the step-down converter is increasing the cur-
rent in the inductor, the high-side MOSFET is on and
current flows in the following path: from C INBP into
INBP >> out of LX >> through the inductor >> into CS
>> out of BAT >> through C BAT and back to C INBP
through the ground plane. This current loop should
be kept small and the electrical length from the posi-
tive terminal of C INBP to INBP should be kept short to
minimize parasitic impedance. The electrical length
from the negative terminal of C BAT to the negative
terminal of C INBP should be short to minimize para-
sitic impedance. Keep all sensitive signals such as
feedback nodes or audio lines outside of this current
loop with as much isolation as your design allows.
3) When the step-down converter is decreasing the
inductor current, the low-side MOSFET is on and
the current flows in the following path: out of LX >>
through the inductor >> into CS >> out of BAT >>
through C BAT >> into PGND >> out of LX again. This
current loop should be kept small and the electrical
length from the negative terminal of C BAT to PGND
should be short to minimize parasitic impedance.
Keep all sensitive signals such as feedback nodes or
audio lines outside of this current loop with as much
isolation as your design allows.
4) The LX node voltage switches between INBP and
PGND during the operation of the step-down con-
verter. Minimize the stray capacitance on the LX node
to maintain good efficiency. Also, keep all sensitive
signals such as feedback nodes or audio lines away
from LX with as much isolation as your design allows.
5) In Figure 14, the CS node is connected to the second
layer of metal with vias. Use low-impedance vias that
are capable of handling 1.5A of current. Also, keep
the routing inductor current path on layer 2 just under-
neath the inductor current path on layer 1 to minimize
impedance.
32
6) Both C BST and C PVL deliver current pulses for the
MAX8900_’s MOSFET drivers. These components
should be placed as shown in Figure 14 to minimize
parasitic impedance.
7) Each of the MAX8900_ bumps has approximately the
same ability to remove heat from the die. Connect as
much metal as possible to each bump to minimize the
B JA associated with the MAX8900_. See the Thermal
Management section for more information on B JA .
In Figure 14, many of the top layer bump pads are con-
nected together in top metal. When connecting bumps
together with top layer metal, the solder mask must
define the pads from 180 F m to 210 F m as shown in
Figure 15. When using solder mask defined pads, please
double check the solder mask openings on the PCB
Gerber files before ordering boards as some PCB lay-
out tools have configuration settings that automatically
oversize solder mask openings. Also, explain in the PCB
fabrication notes that the solder mask is not to be modi-
fied. Occasionally, optimization tools are used at the
PCB fabrication house that modify solder masks. Layouts
that do not use solder mask defined pads are possible.
When using these layouts, adhere to the recommenda-
tions A through G above.
Figure 14. Power PCB Layout Example
Maxim Integrated
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