参数资料
型号: MAX9961BLCCQ-TD
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 比较器
英文描述: Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
中文描述: DUAL COMPARATOR, 100000 uV OFFSET-MAX, 2.2 ns RESPONSE TIME, PQFP100
封装: 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, TQFP-100
文件页数: 16/30页
文件大小: 740K
代理商: MAX9961BLCCQ-TD
MAX9961/MAX9962
Dual, Low-Power, 500Mbps
ATE Drivers/Comparators with 2mA Load
______________________________________________________________________________________
23
SCLK
DIN
D6
D5
D4
D3
D2
D1
D0
tCL
tCSS0
tCSS1
tCSWH
tCSH1
tDH
tDS
tCH
CS
Figure 4. Serial Interface Timing
DQ
ENABLE
SET
1
4
6
F/F
DQ
ENABLE
SET
1
4
5
F/F
0123456
SHIFT REGISTER
DIN
RST
THR
SCLK
ENABLE
CS
DQ
ENABLE
VTHRINT = 1.25V
4
0-3
6
F/F
20k
DQ
ENABLE
4
0-3
5
F/F
LLEAK
LDCAL,
TMSEL,
SC0, SC1
LLEAK
CHANNEL 1 MODE BITS
LDCAL,
TMSEL,
SC0, SC1
CHANNEL 2 MODE BITS
MAX9961
MAX9962
Figure 5. Serial Interface
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9961/MAX9962 into a very-low-leakage
state (see Electrical Characteristics). The comparators
function at full speed, but the driver, clamps, and active
load are disabled. This mode is convenient for making
IDDQ and PMU measurements without the need for an
output disconnect relay. LLEAK is independent for
each channel.
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
ior under this condition.
Serial Interface and Device Control
A CMOS-compatible serial interface controls the
MAX9961/MAX9962 modes (Figure 5). Control data
flow into a 7-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 4.
Data from the shift register are then loaded to either
or both of the latches as determined by bits D5 and
D6, and indicated in Figure 5 and Table 5. The latch-
es contain the 5 mode bits for each channel of the
dual-pin driver. The mode bits, in conjunction with
external inputs DATA_ and RCV_, manage the fea-
tures of each channel, as shown in Figure 2 and
Tables 1 and 2. RST sets LLEAK = 1 for both chan-
nels, forcing them into low-leakage mode. At power-
up, hold RST low until VCC and VEE have stabilized.
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