参数资料
型号: MAXQ610X-0000+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 12 MHz, RISC MICROCONTROLLER, UUC
封装: DIE
文件页数: 15/29页
文件大小: 827K
代理商: MAXQ610X-0000+
MAXQ610
16-Bit Microcontroller with Infrared Module
22
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Operating Modes
The lowest power mode of operation for the MAXQ610
is stop mode. In this mode, CPU state and memories
are preserved, but the CPU is not actively running.
Wake-up sources include external I/O interrupts, the
power-fail warning interrupt, or a power-fail reset. Any
time the microcontroller is in a state where code does
not need to be executed, the user software can put the
MAXQ610 into stop mode. The nanopower ring oscilla-
tor is an internal ultra-low-power (400nA), 8kHz ring
oscillator that can be used to drive a wake-up timer that
exits stop mode. The wake-up timer is programmable
by software in steps of 125s up to approximately 8s.
The power-fail monitor is always on during normal oper-
ation. However, it can be selectively disabled during
stop mode to minimize power consumption. This fea-
ture is enabled using the power-fail monitor disable
(PFD) bit in the PWCN register. The reset default state
for the PFD bit is 1, which disables the power-fail moni-
tor function during stop mode. If power-fail monitoring
is disabled (PFD = 1) during stop mode, the circuitry
responsible for generating a power-fail warning or reset
is shut down and neither condition is detected. Thus,
the VDD < VRST condition does not invoke a reset state.
However, in the event that VDD falls below the POR
level, a POR is generated. The power-fail monitor is
enabled prior to stop mode exit and before code exe-
cution begins. If a power-fail warning condition (VDD <
VPFW) is then detected, the power-fail interrupt flag is
set on stop mode exit. If a power-fail condition is
detected (VDD < VRST), the CPU goes into reset.
Power-Fail Detection
Figures 11, 12, and 13 show the power-fail detection
and response during normal and stop mode operation.
A
B
C
D
F
G
H
I
E
VDD
VPFW
VRST
VPOR
INTERNAL RESET
(ACTIVE HIGH)
t < tPFW
t
≥ tPFW
t
≥ tPFW
t
≥ tPFW
Figure 11. Power-Fail Detection During Normal Operation
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