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参数资料
| 型号： | MB85343C-70 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 1M×32 BIT Hyper Page Mode DRAM Module(CMOS 1M×32位超级页面存取模式动态RAM模块) |
| 中文描述： | 的CMOS 100万× 32位的超页模式内存的CMOS（100万× 32位超级页面存取模式动态内存模块） |
| 文件页数： | 8/11页 |
| 文件大小： | 353K |
| 代理商： | MB85343C-70 |
8
MB85343C-60/MB85343C-70
Notes: 1.
An initial pause (RAS=CAS=V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles or eight CAS-before-RAS refresh cycles (WE=V
IH
) before proper device operation is achieved.
If an internal refresh counter is used, a minimum of eight CAS-before-RAS initialization cycles are
required instead of eight RAS cycles.
AC characteristics assume t
T
= 2 ns.
V
IH
(min.) and V
IL
(max.) are reference levels for measuring the timing of input signals. Transition times
are measured between V
IH
(min.) and V
IL
(max.).
Assumes that t
RCD
≤
t
RCD
(max.), t
RAD
≤
t
RAD
(max.). If t
RCD
and/or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the
value shown.
If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
t
OFF
and t
OFR
are specified that output buffer change to high impedance state.
Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
10. t
RCD
(min.) = t
RAH
(min.)+ 2 t
T
+ t
ASC
(min.).
11. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
13. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min.) the data output pin will remain High-Z
state through entire cycle.
14. t
CPA
is access time from the selection of a new column address (caused by changing CAS from “L” to
“H”). Therefore, if t
CP
become long, t
CPA
also become longer than t
CPA
(max.).
15. Assumes that CAS-before-RAS refresh cycle.
16. Assumes that CAS-before-RAS self refresh cycle.
17. Assumes test mode function.
2.
3.
4.
5.
6.
7.
8.
9.
*Source: See MB814405C Data Sheet for details on the electricals.
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