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参数资料
| 型号： | MB85396A-70 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×36Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×36位 同步动态RAM) |
| 中文描述： | 4米× 36Bit的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 36位同步动态RAM）的 |
| 文件页数： | 7/10页 |
| 文件大小： | 232K |
| 代理商： | MB85396A-70 |
7
MB85396A-60/MB85396A-70
Notes: 1.
An initial pause (RAS = CAS =V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles before proper device operation is achieved. If an internal refresh counter is used, a minimum of
eight CAS-before-RAS initialization cycles are required instead of eight RAS cycles.
AC characteristics assume t
T
= 5 ns.
V
IH
(min) and V
IL
(max) are reference levels for measuring the timing of input signals. Transition times
are measured between V
IH
(min) and V
IL
(max).
Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown.
If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
t
OFF
and t
OEZ
are specified that output buffer change to high impedance state.
Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
10. t
RCD
(min) = t
RAH
(min)+ 2 t
T
+ t
ASC
(min).
11. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
13. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z state
through entire cycle.
14. Assumes that t
WCS
< t
WCS
(min).
15. Either t
DZC
or t
DZO
must be satisfied.
16. t
CPA
is access time from the selection of a new column address (caused by changing CAS from “L” to
“H”). Therefore, if t
CP
become long, t
CPA
also become longer than t
CPA
(max).
17. Assumes that CAS-before-RAS refresh.
18. Assumes that test mode function.
19. t
REF
is for distributed refresh (2,048 refresh cycles/32.8 ms).
2.
3.
4.
5.
6.
7.
8.
9.
*Source: See MB8117400A Data Sheet for details on the electricals.
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