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参数资料
| 型号： | MB88R157A |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8 |
| 文件页数： | 25/28页 |
| 文件大小： | 1186K |
| 代理商： | MB88R157A |
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MB88R157A
6
DS04-29146-1E
■ MEMORY MAP
(Continued)
Address
Function
Remarks
bit0, bit1
VF pin function setting
The function for the VF pin (pin 6) is selectable.
00 : No modulation, 01 : Output selection function,
10 : Modulation control, 11 : Power down control
bit2 to bit8
XIN oscillation stabilization
capacitance setting (7-bit)
Capacitance is selectable from 5 pF to 10 pF by
0.039 pF Step
bit9 to bit15
XOUT oscillation stabilization
capacitance setting (7-bit)
Capacitance is selectable from 5 pF to 10 pF by
0.039 pF Step
Setting
1
bit16 to bit27
M divider setting 1 (12-bit)
Selectable in the range of 2 to 4095
bit28 to bit38
N divider setting 1 (11-bit)
Selectable in the range of 2 to 2047
bit39 to bit45
K divider setting 1 (7-bit)
Selectable in the range of 1 to 128
bit46 to bit48
L divider setting 1 (3-bit)
Modulation frequency setting
(the value is due to the input frequency)
bit49 to bit52
Charge Pump setting 1 (4-bit)
Charge pump current setting due to VCO oscillation
frequency
bit53 to bit57
VCO Gain setting 1 (5-bit)
VCO gain setting due to VCO oscillation frequency
bit58 to bit61
Modulation rate setting 1
(4-bit)
No modulation,
±0.125%, ±0.25%, ±0.50%, ±0.75%,
±1.00%, ±1.25%, ±1.50%, ±1.75% are selectable
bit62
Output drive ability setting 1
0: Ability small, 1: Ability large
bit63
Output slew rate ability setting 1 0 : Slew rate low, 1 : Slew rate high
bit64
OUT pin setting 1
Selectable OUT pin situation at OE pin = L and power
down
0 : L output, 1 : Hi-Z output
bit65
Source clock dividing mode 1
Source clock for K divider is selectable.
0 : VCO output , 1 : Source clock
bit66
PLL mode 1
0 : Normal mode, 1 : PLL mode
bit67
Input clock setting 1
0 : External clock input, 1 : Crystal oscillator
bit68 to bit71
Reserve
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