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参数资料
| 型号： | MB88R157A |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8 |
| 文件页数： | 26/28页 |
| 文件大小： | 1186K |
| 代理商： | MB88R157A |
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MB88R157A
DS04-29146-1E
7
(Continued)
Address
Function
Remarks
Setting
2
bit72 to bit83
M divider setting 2 (12-bit)
Selectable in the range of 2 to 4095
bit84 to bit94
N divider setting 2 (11-bit)
Selectable in the range of 2 to 2047
bit95 to bit101
K divider setting 2 (7-bit)
Selectable in the range of 1 to 128
bit102 to bit104 L divider setting 2 (3-bit)
Modulation frequency setting (the value is due to the
input frequency)
bit105 to bit108 Charge Pump setting 2 (4-bit)
Charge pump current setting due to VCO oscillation
frequency
bit109 to bit113 VCO Gain setting 2 (5-bit)
VCO gain setting due to VCO oscillation frequency
bit114 to bit117
Modulation rate setting 2
(4-bit)
No modulation,
±0.125%, ±0.25%, ±0.50%, ±0.75%,
±1.00%, ±1.25%, ±1.50%, ±1.75% are selectable
bit118
Output drive ability setting 2
0: Ability small, 1: Ability large
bit119
Output slew rate ability setting 2 0 : Slew rate low, 1 : Slew rate high
bit120
OUT pin setting 2
Selectable OUT pin situation at OE pin = L and power
down
0 : L output, 1 : Hi-Z output
bit121
Source clock dividing mode 2
Source clock for K divider is selectable.
0 : VCO output , 1 : Source clock
bit122
PLL mode 2
0 : Normal mode, 1 : PLL mode
bit123
Input clock setting 2
0 : External clock input, 1 : Crystal oscillator
bit124 to bit127
Reserve
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