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参数资料
| 型号： | MB88R157A |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8 |
| 文件页数： | 4/28页 |
| 文件大小： | 1186K |
| 代理商： | MB88R157A |
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MB88R157A
12
DS04-29146-1E
pa
■ MEMORY ACCESS
The non-volatile memory contained in this device can read/write using the serial communication that the SP pin
works as the I/O pin.
The communication protocol needs to set LSB first, NRZ format, 8-bit length, no parity and stop bit length 1-bit
in the UART asynchronous transfer mode. The transfer speed needs to be set to 1/512 of the device source
oscillation.
1. More than 50 ms after this device is turned on, input a command from the SP pin and set MB88R157A into
memory access mode.(When a command is input by serial communication, data of “FDH” is sent.)
Note: When memory access is available, source clock can be output from the OUT pin.
Fix the SP pin to “H” or “L” until command input.
2. At writing, “00H” is sent serially, and at reading, “40H” is sent serially.
Note: This device needs to stop outputting to the OE pin of the transferred device within 9
μs after transferring
“40H” serially at the reading state and place it to a receivable state.
3. At writing : Send 16-byte data blocks from the lower address of the memory map in turn with more than 30
μs
between each data block.
At reading : This device outputs 16-byte data blocks from the lower address of the memory map in turn.
Note: 16-byte is required to transfer data even if setting 2 is not used.
4. Repeat the operations of 2. and 3. for re-writing and re-reading.
To operate the device using the written data, turn on the power again.
However, the oscillation stabilization capacitance is set simultaneously with writing to memory. When the
oscillation stabilization capacitance and the crystal oscillation frequency are adjusted, change the oscillation
stabilization capacitance value so that the clock output from the OUT pin is set to the desired frequency.
VDD
SP
50 ms
2.5 V
OUT
Memory access
mode signal
(internal)
Source clock output
Transfer sequence
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