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参数资料
| 型号： | MB88R157A |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 4.40 X 3.10 MM, 1.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, TSSOP-8 |
| 文件页数： | 28/28页 |
| 文件大小： | 1186K |
| 代理商： | MB88R157A |
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MB88R157A
DS04-29146-1E
9
Output drive ability setting
The output drive ability of the OUT pin can be selected.
Output slew rate ability setting
The output slew rate ability of the OUT pin can be selected.
OUT pin setting
The OUT pin situation can be selected at OE pin “L” input and power down.
Note : Internal oscillation circuit has been operating even if the OE pin is inputting “L”.
Source clock dividing setting
Source clock for K divider can be selected.
When “input frequency” is selected, source clock or its divided clock can be output. But modulation setting is
not enabled.
PLL mode setting
It can be selected from normal mode and PLL mode by bit48 setting in the memory map. PLL mode is good
jitter specification at non modulation. When the mode is selected, it becomes non modulation setting, the
resistance and capacitance value of the loop filter is changed, so oscillation specification will change.
When PLL mode is selected, the recommended value of M, N, K divider is changed. Please refer and confirm
the recommended value by our support tool. Contact the sales representatives for details on the support tools.
bit62, bit118
OUT pin drive ability
0
Small (IOL
= 4 mA)
1
Large (IOL
= 8 mA)
bit63, bit119
OUT pin slew rate ability
0
Slew rate low
1Slew rate high
bit64, bit120
OUT pin situation
0
“L” output
1
“Hi-Z” output
bit65, bit121
Source clock for K divider
0
VCO output clock
1
Input clock (Source clock)
bit66, bit122
Operation mode
0
SSCG mode
1
PLL mode
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