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参数资料
| 型号： | MB89T635P-SH |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封装： | SHRINK, DIP-64 |
| 文件页数： | 106/153页 |
| 文件大小： | 7326K |
| 代理商： | MB89T635P-SH |
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HARDWARE CONFIGURATION
2-33
P40 to P43 CMOS-type I/O ports (also used as resource input/output)
Switching input and output
This port has a data-direction register (DDR) and a port-data register (PDR) for each bit. Input and out-
put can be set independently for each bit. The pin with the DDR set to 1 is set to output, and the pin with
the DDR set to 0 is set to input. When the resource-output enable bit is enabled, the pin is set to output
irre spective of the DDR setting conditions.
Operation for output port (DDR = 1)
The value written at the PDR is output to the pin when the DDR is set to 1. When the PDR is read, usu-
ally, the value of the pin is read instead of the contents of the output latch. However, when the Read
Modify Write instruction is executed, the contents of the output latch are read irrespective of the DDR
setting con ditions. Therefore, the bit-processing instruction can be used even if input and output are
mixed with each other. When data is written to the PDR, the written data is held in the output latch irre-
spective of the DDR setting conditions.
Operation for input port (DDR = 0)
When used as the input port, the output impedance goes High. Therefore, when the PDR is read, the
value of the pin is read.
Operation for resource output
When using as the resource output, setting is performed by the resource output- enable bit. (See the de
scription of each resource.) If the output of each resource is enabled with the DDR set to 0, the port is
set to output. Since the reading of the parallel port is effective even if the output of each resource is
enabled, the output value of each resource can be read.
Operation for resource input
Input to the resource is irrelevant to the setting conditions of the DDR and resource. The value of the pin
is always input to the port serving as the resource input. When using an external signal at the resource,
set the DDR to input.
State when reset
When reset, the DDR and resource output-enable bit are initialized to 0 and the output impedance goes
High at all bits. (Pins with activated pull-up resistors are in the pull-up state.) When reset, the PDR is
unde fined. Therefore, set the value of the PDR before setting the DDR to output.
State in stop mode
With the SPL bit of the standby-control register set to 1, in the stop mode, the output impedance goes
High irrespective of the value of the DDR. (Pins with activated pull-up resistors are in the pull-up state.)
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