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参数资料
| 型号： | MB90561PFM |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 32/91页 |
| 文件大小： | 931K |
| 代理商： | MB90561PFM |
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MB90560/565 Series
38
5.
Multi-Function Timer
Based on the 16-bit freerun timer, the multi-function timer can be used to generate 12 independent waveform
outputs and to measure input pulse widths and external clock periods.
Structure of multi-function timer
16-bit freerun timer (1 channel)
The 16-bit freerun timer consists of a 16-bit up-counter (timer data register (TCDT) ) , compare clear register
(CPCLR) , timer control status register (TCCS) , and prescaler.
The count output value from the 16-bit freerun timer provides the base time for the input capture and output
compare functions.
The count clock can be selected from the following eight clocks :
1/
φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ
φ : Machine clock frequency
An interrupt can be generated when the 16-bit freerun timer overflows or when the 16-bit freerun timer count
is cleared to “0000H” due to a match occurring between the value in the compare clear register (CPCLR) and
the count in the 16-bit freerun timer (TCCS : ICRE
= “1”, MODE = “1”) .
The 16-bit freerun timer is cleared to “0000H” when a reset occurs, on setting the timer clear bit (SCLR) in the
timer control status register (TCCS) , when a compare match occurs between the 16-bit freerun timer count
and the value in the compare clear register (CPCLR) (TCCS : MODE
= “1”) , or by writing “0000H” to the timer
data register (TCDT) .
Output compare (6 channels)
The output compare unit consists of compare registers (OCCP0 to OCCP5) , compare control registers (OCS0
to OCS5) , and compare output latches.
When a match occurs between a compare register (OCCP0 to OCCP5) value and the count from the 16-bit
freerun timer, the output compare can invert the level of the corresponding output compare pin and generate
an interrupt.
The compare registers (OCCP0 to OCCP5) operate independently for each channel. Each of the compare
registers (OCCP0 to OCCP5) has a corresponding output pin and an interrupt request flag in the channel’s
compare control register (lower) (OCS0, OCS2, OCS4) .
Two channels of the compare registers (OCCP0 to OCCP5) can be used to invert the output pins.
An interrupt can be output when a match occurs between a compare register (OCCP0 to OCCP5) and the
count from the 16-bit freerun timer (OCS0, OCS2, OCS4 : IOP0
= “1”, IOP1 = “1”) . (OCS0, OCS2, OCS4 :
IOE0
= “1”, IOE1 = “1”)
The initial output levels for the output compare pins can be set.
Input capture (4 channels)
The input capture consists of external input pins (IN0 to IN3) , corresponding input capture data registers (IPCP0
to IPCP3) , and input capture control status registers (ICS01, ICS23) .
The input capture can transfer the count value from the 16-bit freerun timer to the input capture data register
(IPCP0 to IPCP3) and output an interrupt on detecting an active edge on the signal input from the external input
pin.
Each channel of the input capture operates independently.
The active edge (rising edge, falling edge, or either edge) on the external signal can be specified.
16-bit
freerun timer
16-bit
output compare
16-bit
input capture
8/16-bit
PPG timer
Waveform
generator
1 ch
6 ch
4 ch
8 bit
× 6 ch
16 bit
× 3 ch
8-bit timer
× 3 ch
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB90562 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
| MB90562A | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
| MB90562AP | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
| MB90562APF | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
| MB90562APFM | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
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