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参数资料
| 型号： | MB90561PFM |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 42/91页 |
| 文件大小： | 931K |
| 代理商： | MB90561PFM |
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MB90560/565 Series
47
7.
DTP/External Interrupt Circuit
(1) Overview of the DTP/external interrupt circuit
The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external
interrupt input pins (INT7 to INT0) and outputs interrupt requests.
DTP/external interrupt circuit functions
The DTP/external interrupt function detects edge or level signals input to the external interrupt input pins (INT7
to INT0) and outputs interrupt requests.
The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI2OS) is enabled,
EI2OS performs automatic data transfer (DTP function) then passes control to the interrupt handler routine on
completion. If EI2OS is disabled, control passes directly to the interrupt handler routine without performing
automatic data transfer (DTP function) .
Overview of the DTP/external interrupt circuit
DTP/external interrupt circuit interrupts and EI2OS
: Available when the interrupt shared with ICR07 or ICR08 is not used.
Channel
Interrupt
No.
Interrupt Control Register
Vector Table Address
EI2OS
Register Name
Address
Lower
Upper
Bank
INT0/INT1
#25 (19H)
ICR07
0000B7H
FFFF98H
FFFF99H
FFFF9AH
INT2/INT3
#26 (1AH)
FFFF94H
FFFF95H
FFFF96H
INT4/INT5
#27 (1BH)
ICR08
0000B8H
FFFF90H
FFFF91H
FFFF92H
INT6/INT7
#28 (1CH)
FFFF8CH
FFFF8DH
FFFF8EH
ICR : Interrupt control register
External Interrupt
DTP Function
Input pins
8 channels (P10/INT0 to P16/INT6, P63/INT7)
Interrupt conditions
The level or edge to detect can be set independently for each pin in the detection lev-
el setup register (ELVR) .
“L” level, “H” level, rising edge, or falling edge input
Interrupt number
#25 (19H) to #28 (1CH)
Interrupt control
Interrupts can be enabled or disabled in the DTP/external interrupt enable register
(ENIR) .
Interrupt flag
The DTP/external interrupt request register (ENRR) stores interrupt requests.
Processing selection
Set EI2OS to disabled (ICR : ISE
= 0)
Set EI2OS to enabled (ICR : ISE
= 1)
Operation
Jumps to interrupt handler routine
Jumps to interrupt handler routine after
automatic data transfer by EI2OS com-
pletes.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB90562 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontrollers |
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