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参数资料
| 型号： | MB95D108AWPFV |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 53/67页 |
| 文件大小： | 824K |
| 代理商： | MB95D108AWPFV |
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MB95100A Series
57
(Continued)
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 :
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n)
= (1, 8)
: 0.9 MHz < tMCLK
≤ 1 MHz
(m, n)
= (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n)
= (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n)
= (1, 98)
: 0.9 MHz < tMCLK
≤ 10 MHz
Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n)
= (1, 8)
: 3.3 MHz < tMCLK
≤ 4 MHz
(m, n)
= (1, 22) , (5, 4)
: 3.3 MHz < tMCLK
≤ 8 MHz
(m, n)
= (6, 4)
: 3.3 MHz < tMCLK
≤ 10 MHz
Parameter
Sym-
bol
Pin
name
Condi-
tions
Value*2
Unit
Remarks
Min
Max
Stop condition
detection
tSU;STO
SCL0
SDA0
R
= 1.7 k,
C
= 50 pF*1
2 tMCLK
20
ns
Undetected when 1
tMCLK is used at
reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when 1
tMCLK is used at
reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK
20
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 tMCLK
20
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW
3 tMCLK 20
ns
At slave transmission
mode
Data hold time
tHD;DAT
SCL0
SDA0
0
ns
At reception
Data setup time
tSU;DAT
SCL0
SDA0
tMCLK
20
ns
At reception
SDA
↓→SCL↑
(at wakeup function)
tWAKE-
UP
SCL0
SDA0
Oscillation stabilization
wait time
+
2 tMCLK
20
ns
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