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| 型号： | MB9BF504NPMC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 20/120页 |
| 文件大小： | 1277K |
| 代理商： | MB9BF504NPMC |
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116
8266D-MCU Wireless-06/12
ATmega128RFA1
If enabled, pin DIG1 and pin DIG2 become output pins and provide a differential control
signal for an external Antenna Diversity switch. The selection of a specific antenna is
done either by the automatic Antenna Diversity algorithm (ANT_DIV_EN = 1) or
according to bits ANT_CTRL if the Antenna Diversity algorithm is disabled. Do not
enable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame
Time Stamping (IRQ_2_EXT_EN = 1, see register TRX_CTRL_1) at the same time. If
this bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as
long as bit ANT_EXT_SW_EN is also set. If the radio transceiver is not in a receive or
transmit state, it is recommended to disable bit ANT_EXT_SW_EN to reduce the power
consumption or avoid leakage current of an external RF switch especially during
SLEEP state. If bit ANT_EXT_SW_EN = 0, the output pins DIG1 and DIG2 are
controlled by the register of I/O ports F and G (PORTF, DDRF, PORTG, DDRG).
Table 9-49 ANT_EXT_SW_EN Register Bits
Register Bits
Value
Description
0
Antenna Diversity RF switch control disabled
ANT_EXT_SW_EN
1
Antenna Diversity RF switch control enabled
Bit 1:0 – ANT_CTRL1:0 - Static Antenna Diversity Switch Control
These bits provide a static control of an Antenna Diversity switch. This register setting
defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled).
Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1.
Table 9-50 ANT_CTRL Register Bits
Register Bits
Value
Description
0
Reserved
1
Antenna 1: DIG1=L, DIG2=H
2
Antenna 0: DIG1=H, DIG2=L
ANT_CTRL1:0
3
Default value for ANT_EXT_SW_EN=0;
Mandatory setting for applications not using
Antenna Diversity
9.12.18 IRQ_MASK – Transceiver Interrupt Enable Register
Bit
7
6
5
4
NA ($14E)
AWAKE_EN
TX_END_EN
AMI_EN
CCA_ED_DONE_EN
IRQ_MASK
Read/Write
RW
Initial Value
0
Bit
3
2
1
0
NA ($14E)
RX_END_EN
RX_START_EN
PLL_UNLOCK_EN
PLL_LOCK_EN
IRQ_MASK
Read/Write
RW
Initial Value
0
This register is used to enable or disable individual interrupts of the radio transceiver.
An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled
after the power up sequence or reset. If an interrupt is enabled it is recommended to
read the interrupt status register IRQ_STATUS first to clear the history.
Bit 7 – AWAKE_EN - Awake Interrupt Enable
Bit 6 – TX_END_EN - TX_END Interrupt Enable
Bit 5 – AMI_EN - Address Match Interrupt Enable
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