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参数资料
型号： MB9BF504NPMC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封装： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数： 66/120页
文件大小： 1277K
代理商： MB9BF504NPMC
MB9B500 Series
Dual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
·
Free-running
·
Periodic (=Reload)
·
One-shot
Watch Counter
The Watch counter is used for wake up from power saving mode.
·
Interval timer: up to 64s(Max.)@ Sub Clock : 32.768kHz
External Interrupt Controller Unit
·
Up to 16 external vectors
·
Include one non-maskable interrupt(NMI)
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
MB9B500 series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed CR oscillator. Therefore,”Hardware" watchdog is
active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
·
CCITT CRC16 Generator Polynomial: 0x1021
·
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and PLL) that are dynamically selectable.
·
Main Clock
: 4 to 48MHz
·
Sub Clock
: 32.768kHz
·
High-speed CR Clock : 4MHz
·
Low-speed CR Clock : 100kHz
·
PLL Clock
[Resets]
Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low voltage
detector reset and clock supervisor reset.
Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
·
External OSC clock failure (clock stop) is detected, reset is asserted.
·
External OSC frequency anomaly is detected, interrupt or reset is asserted.
5
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r5.0
DS706-00010-1v0-E
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相关代理商/技术参数
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