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参数资料
| 型号： | MC-ACT-16550-NET |
| 元件分类： | FPGA |
| 英文描述： | FPGA, XMA |
| 文件页数： | 2/9页 |
| 文件大小： | 278K |
| 代理商： | MC-ACT-16550-NET |
Functional Description
The diagram on the rst page shows the Block Diagram of the MC-ACT-16550 Core. The core is partitioned into modules. These modules are described below.
INTERFACE CONTROL LOGIC
The core is congured via a conguration vector (CFG[127:0]). This vector contains information required for proper operation of the core. The command vector input
(TWSI_CMD[2:0]) is used to instruct the core what operation to perform. The contents of the input and output vectors are as follows:
Conguration Vector
Applicable to the following core congurations:
Master-Only
Master-Slave
Slave-Only
Yes
The bits of the Conguration Vector are dened as follows:
Conguration Bits
Description
CFG[6:0]
TWSI Slave’s Own Address
CFG[7]
Reserved
CFG[19:8]
SCL BusFree (arbitration) Timer Value for Standard Speed
CFG[31:20]
SCL HI Timer Value for Standard Speed
CFG[43:32]
SCL LO Timer Value for Standard Speed
CFG[45:44]
TWSI Mode (Master-Only, Slave-Only, Master-Slave)
CFG[46]
Enable the SCL Glitch Filters
CFG[47]
Enable two extra CLK periods of hold time on SDA from the falling edge of SCL.
CFG[48]
Enable General Call Addressing
CFG[60:49]
SCL BusFree (arbitration) Timer Value for Fast Speed
CFG[72:61]
SCL HI Timer Value for Fast Speed
CFG[84:73]
SCL LO Timer Value for Fast Speed
CFG[127:85]
Reserved
Table 1: Conguration Vector
Command Vector
Applicable to the following core congurations:
Master-Only
Master-Slave
Slave-Only
Yes
Undened
The bits in this vector are dened as follows:
2
1
0
RESTART
STOP
READ
Figure 1: Command Vector
These three bits of the command vector control the operation performed on the serial interface. The READ bit determines if the operation will be a read (high) or a
write (low). The STOP bit will determine if the cycle will stop at the end of the data cycle, or continue on to a burst. The REPEATED START bit will cause the genera-
tion of a repeated start protocol.
相关PDF资料 |
PDF描述 |
|---|---|
| MC-ACT-16550-VLOG | FPGA, XMA |
| MC00S2NZQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC00S3NCQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
| MC07L2NZGD | ROTARY SWITCH-7POSITIONS, SP7T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC12S1NZGF | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC-ACT-16550-VLOG | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Two Wire Serial Interface (TWSI) |
| MC-ACT-6809 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-VHD | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-G704E1-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ISDN Terminal Equipment E2 Interface (multi G704 on chip) E1-ATM Interface |
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