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参数资料
| 型号： | MC-ACT-16550-NET |
| 元件分类： | FPGA |
| 英文描述： | FPGA, XMA |
| 文件页数： | 5/9页 |
| 文件大小： | 278K |
| 代理商： | MC-ACT-16550-NET |
SHIFT LOGIC
The basic cycle on the TWSI serial interface consists of an address cycle followed by data cycle(s). The address consists of seven bits and the read/write bit (the
LSB). The MSB is always transmitted rst on the SDA line. The data cycle can either be a read or a write. For a write operation, the core shifts the data from the
DATA_IN Register onto the SDA line. For a read operation, the core captures the data into the Shift Register. The host can read the Shift Register contents via the
DATA_OUT Register. The data cycle can end in three different ways:
1. A stop can be generated which terminates the current cycle
2. Another data cycle can take place (a burst)
3. A repeated start can be generated by the interface
For each byte read, DATA_VLD will be asserted for one clock to tell the host that valid data is on DATA_OUT. For each byte written, REQ_DATA will be asserted for
one clock to ask the host for another byte of data to send.
A repeated start is used to turn the bus around; when a read cycle must be followed directly by a write cycle without a stop in-between. Since the READ bit is a part
of the address, if a read followed by write is desired without a stop command, a second address must be issued following the data cycle. The sequence of events in a
repeated start cycle is: start, address cycle, data cycle, repeated start, address cycle, data cycle, stop. Each of the data cycles can be repeated if bursting is desired,
and the stop cycle could actually be another repeated start, if desired.
GENERAL CALL ADDRESSING
The General Call Address is used to address and send data to every node on the I2C bus and is enabled by bit 48 of the conguration vector (CFG[48]). Not all
devices are required to support General Call. Nodes not requiring the data sent within a General Call data transfer can ignore the transfer by not acknowledging the
address. If a node does require the data sent with a General Call it will acknowledge the address and behave as a slave receiver for the subsequent bytes. If any
given slave cannot process any of the subsequent bytes during the transfer, it must ignore the byte by not acknowledging. The behavior for a General Call transfer is
specied in the second byte, and is determined by the LSB.
When the LSB of the second byte is a ‘0’, the second byte can have the following denition:
“00000110” (H’06’) – Write the slave address (the third byte to be sent) and then reset. All devices receiving this two-byte sequence will treat the third byte to be sent
as their new I2C address and will then reset. Care must be taken by the slave nodes not to drive (pull down) the SDA or SCL lines while resetting to avoid blocking
the bus.
“00000100” (H’04’) – Write the slave address (the third byte to be sent) and do not reset. All devices receiving this two-byte sequence will treat the third byte to be
sent as their new I2C address. The node will not reset.
“00000000” (H’00’) – This byte is not allowed to be sent as the second byte.
All other bytes in the second byte of the transfer have not been specied and nodes are generally required (per the Philips I2C specication) to ignore them.
When the LSB of the second byte is a ‘0’, the second byte will be a ‘Hardware General Call’. This means that a master node on the I2C, which cannot be pro-
grammed to send a specic slave address, needs the attention of another node to facilitate a transfer. This is typical of embedded hardware nodes such as keyboard
scanners. Since a hardware master can’t be programmed to address a specic node to which it needs to transfer data, it can only initiate a General Call followed
by its own address to identify itself to the system. The seven upper bits of the second byte contain the address of the hardware master. An intelligent device then
recognizes this address on the I2C bus, which will direct the information from the hardware master.
相关PDF资料 |
PDF描述 |
|---|---|
| MC-ACT-16550-VLOG | FPGA, XMA |
| MC00S2NZQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC00S3NCQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
| MC07L2NZGD | ROTARY SWITCH-7POSITIONS, SP7T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC12S1NZGF | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC-ACT-16550-VLOG | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Two Wire Serial Interface (TWSI) |
| MC-ACT-6809 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-VHD | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-G704E1-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ISDN Terminal Equipment E2 Interface (multi G704 on chip) E1-ATM Interface |
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