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参数资料
| 型号： | MC-ACT-16550-NET |
| 元件分类： | FPGA |
| 英文描述： | FPGA, XMA |
| 文件页数： | 4/9页 |
| 文件大小： | 278K |
| 代理商： | MC-ACT-16550-NET |
Slave Only
5
4
3
2
1
0
HDWE_GC
GC_RST
GC_ADDR
GC_BUSY
Not
Implemented
Not
Implemented
Figure 4: Status Vector
Bit 5 - HDWE_GC: Indicates the core has received the Hardware General Call instruction.
Bit 4 - GC_RST: Indicates the core has received General Call instruction to reset and change its address.
Bit 3 - GC_ADDR: Indicates the core has received General Call instruction to change its address.
Bit 2 - GC_BUSY: Indicates the core is busy with a General Call access.
Bit 1 - BUSLOSS: Indicates that this master lost the bus to another master before completion of the cycle.
Bit 0 - SLAVE_TIMEOUT: Indicates that the addressed slave did not respond with a nack when required.
Data Output Vector
Applicable to the following core congurations:
Master-Only
Master-Slave
Slave-Only
Yes
The bits in this vector are dened as follows:
7
6
5
4
3
2
1
0
DATA_OUT[7]
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
Figure 5: Data Output Vector
The data output vector (DATA_OUT[7:0]) contains the data from the receive shift register
SHIFT REGISTER
There is a single parallel-in, parallel-out, serial-in, serial-out shift register called NUPSHIFT, which performs the shifting of data for address cycles, write cycles, and
read cycles. The parallel output drives the core interface pins DATA_OUT, which are used to return read data to the host.
SYNCHRS
The SDA and SCL inputs are passed through the Synchrs module that performs a dual-rank synchronization and glitch ltering when enabled by bit 46 of the congu-
ration vector (CFG[46]).
The MC-TWSI core treats both the SDA and SCL lines as data lines. The SDA line is actually sampled some number of clocks after the rising edge of SCL is de-
tected. This allows for greater noise immunity and more robust operation.
STATE MACHINE
The control for the serial interface comes from the TWSI_SM_M, TWSI_SM_S, and GEN_CALL_SM state machines. These state machines control the loading and
enabling of all shift registers and counters, and are responsible for implementing the basic interface protocol.
Arbitration
Before the MC-TWSI initiates either a start or repeated start condition, it samples the synchronized versions of SDA and SCL for BUSFREE_COUNT x clock periods
of high values. If at any time either of these pins is detected in a low (driven) state, then the count starts over (it assumes that another master is on the bus). The
automatic retrying to obtain the serial bus only occurs until the start command is issued. After that, the responsibility of the retry is left to software, since cycles may
be of innite length.
After a start is issued and while the address or data is being written to the slave, the macro samples the data on the SDA pin while SCL is high. If a data mismatch is
detected then the operation is aborted with an interrupt and a BUSLOSS status. This can also occur during burst reads whenever a NACK is intended to be issued
and an ACK is detected instead.
相关PDF资料 |
PDF描述 |
|---|---|
| MC-ACT-16550-VLOG | FPGA, XMA |
| MC00S2NZQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC00S3NCQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC-ACT-16550-VLOG | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Two Wire Serial Interface (TWSI) |
| MC-ACT-6809 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-VHD | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-G704E1-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ISDN Terminal Equipment E2 Interface (multi G704 on chip) E1-ATM Interface |
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