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参数资料
| 型号： | MC-ACT-16550-NET |
| 元件分类： | FPGA |
| 英文描述： | FPGA, XMA |
| 文件页数： | 7/9页 |
| 文件大小： | 278K |
| 代理商： | MC-ACT-16550-NET |
Application
BASIC INTERFACE OPERATION
All I/O to and from the TWSI core is synchronous to the system clock, CLK.
Before any operation of the MC-TWSI core, the ENABLE must rst be asserted. This must be done via a register on the host interface.
For a TWSI master to initiate a transaction on the bus, the host sets up the ADDR_IN, DATA_IN and TWSI_CMD ports and strobes the START input for one clock and
performs other operations until either REQ_DATA (in the case of a write) or DATA_VLD (in the case of a read) is asserted. Also, the SLAVE_TIMEOUT (STATUS[0])
and BUSLOSS (STATUS[1]) bits should be polled in case the slave does not respond or the master loses arbitration. The BUSLOSS status bit will be asserted if the
interface lost the bus to another master before completion of the cycle. The SLAVE_TIMEOUT bit will be asserted if the slave does not respond with a NACK when
required. For either of these error conditions, the host must retry the current cycle by strobing START. Note that for burst operations the host is responsible for writing
the incremented address into the ADDRESS Register before retrying the operation.
HOST WRITE OPERATION
The following gure shows how the microprocessor interface connects to the internal control registers:
Figure 6: Host Write Register Interface
On the rising edge of CLK, the values on DATA_IN[7:0] and ADDR_IN[6:0] and TWSI_CMD[2:0] is clocked into their registers when START is strobed.
Figure 7: Input Register Timing
Notice in Figure 7 that START acts as the write enable for the registers. Also notice that when CLK samples START asserted, the STATUS bits are cleared on the
next rising edge of CLK.
CLK
MDS2108a
DATA_IN[7:0]
ADDR_IN[6:0]
START
Valid
"000000"
Old Value
STATUS
Valid
TWSI_CMD[2:0]
Valid
8
D Q
CE
DATA_IN[7:0]
START
data_in_r[7:0]
7
D Q
CE
addr_in_r[6:0]
3
D Q
CE
twsi_cmd_r[2:0]
CLK
MDS2105
ADDR_IN[6:0]
TWSI_CMD[2:0]
相关PDF资料 |
PDF描述 |
|---|---|
| MC-ACT-16550-VLOG | FPGA, XMA |
| MC00S2NZQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC00S3NCQD | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
| MC07L2NZGD | ROTARY SWITCH-7POSITIONS, SP7T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MC12S1NZGF | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC-ACT-16550-VLOG | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Two Wire Serial Interface (TWSI) |
| MC-ACT-6809 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-6809-VHD | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Software Compatible 6809 CPU |
| MC-ACT-G704E1-NET | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ISDN Terminal Equipment E2 Interface (multi G704 on chip) E1-ATM Interface |
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