参数资料
型号: MC100ES6226AC
厂商: IDT, Integrated Device Technology Inc
文件页数: 1/9页
文件大小: 0K
描述: IC CLK BUFF DVDR 1:9 3GHZ 32LQFP
标准包装: 250
系列: 100ES
类型: 扇出缓冲器(分配),除法器
电路数: 1
比率 - 输入:输出: 1:9
差分 - 输入:输出: 是/是
输入: LVCMOS,LVPECL
输出: LVPECL
频率 - 最大: 3GHz
电源电压: 2.375 V ~ 3.465 V
工作温度: 0°C ~ 110°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
其它名称: 800-2002
MC100ES6226ACIDT-ND
DATASHEET
2.5v/3.3v Differential LVPECL 1:9
Clock Distribution Buffer and Clock Driver
MC100ES6226
MC100ES6226 DECEMBER 18, 2012
1
2012 Integrated Device Technology, Inc.
The MC100ES6226 is a bipolar monolithic differential clock distribution buffer and clock
divider. Designed for most demanding clock distribution systems, the MC100ES6226
supports various applications requiring a large number of outputs to drive precisely aligned
clock signals. Using SiGe technology and a fully differential architecture, the device offers
superior digital signal characteristics and very low clock skew error. Target applications for
this clock driver are high performance clock distribution systems for computing,
networking and telecommunication systems.
Features
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Selectable 1:1 or 1:2 frequency outputs
LVPECL compatible differential clock inputs and outputs
LVCMOS compatible control inputs
Single 3.3V or 2.5V supply
Max. 35ps maximum output skew (within output bank)
Max. 50ps maximum device skew
Supports DC operation and up to 3GHz (typ.) clock signals
Synchronous output enable eliminating output runt pulse generation and metastability
Standard 32-lead LQFP package
Industrial temperature range (-40°C TO 85°C)
32-lead Pb-free package available
Functional Description
MC100ES6226 is designed for very skew critical differential clock distribution systems
and supports clock frequencies from DC up to 3.0GHz. Typical applications for the
MC100ES6226 are primary clock distribution systems on backplanes of high-performance
computer, networking and telecommunication systems, as well as on-board clocking of
OC-3, OC-12 and OC-48 speed communication systems.
The MC100ES6226 can be operated from a 3.3V or 2.5V positive supply without the
requirement of a negative supply line. Each of the output banks of three differential clock
output pairs may be independently configured to distribute the input frequency or half of
the input frequency. The FSEL0 and FSEL1 clock frequency selects are asynchronous
control inputs. Any changes of the control inputs require a MR pulse for re-synchronization
of the
2 outputs.
2.5 V/3.3 V DIFFERENTIAL
LVPECL 1:9 CLOCK DISTRIBUTION
BUFFER AND CLOCK DIVIDER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
ORDERING INFORMATION
Device
Package
MC100ES6226FA
LQFP-32
MC100ES6226FAR2
LQFP-32
MC100ES6226AC
LQFP-32 (Pb-Free)
MC100ES6226ACR2
LQFP-32 (Pb-Free)
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
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