- 您现在的位置：买卖IC网 > PDF目录8751 > MC100ES6226AC (IDT, Integrated Device Technology Inc)IC CLK BUFF DVDR 1:9 3GHZ 32LQFP PDF资料下载
参数资料
| 型号： | MC100ES6226AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF DVDR 1:9 3GHZ 32LQFP |
| 标准包装： | 250 |
| 系列： | 100ES |
| 类型： | 扇出缓冲器（分配），除法器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:9 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | LVCMOS，LVPECL |
| 输出： | LVPECL |
| 频率 - 最大： | 3GHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | 0°C ~ 110°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
| 其它名称： | 800-2002 MC100ES6226ACIDT-ND |
MC100ES6226 REVESION 5 DECEMBER 18, 2012
7
2012 Integrated Device Technology, Inc.
MC100ES6226 Data Sheet
2.5V/3.3V DIFFERENTIAL LVPECL 1:9 CLOCK DISTRIBUTION BUFFER AND CLOCK DRIVER
Figure 4. MC100ES6226 AC Test Reference
APPLICATIONS INFORMATION
Maintaining Lowest Device Skew
The MC100ES6226 guarantees low output-to-output bank
skew of 35ps and a part-o-part skew of max. TBDps. To ensure
low skew clock signals in the application, both outputs of any
differential output pair need to be terminated identically, even if
only one output is used. When fewer than all nine output pairs are
used, identical termination of all output pairs within the output
bank is recommended. If an entire output bank is not used, it is
recommended to leave all of these outputs open and
unterminated. This will reduce the device power consumption
while maintaining minimum output skew.
Power Supply Bypassing
The MC100ES6226 is a mixed analog/digital product. The
differential architecture of the MC100ES6226 supports low noise
signal operation at high frequencies. In order to maintain its
superior signal quality, all VCC pins should be bypassed by high-
frequency ceramic capacitors connected to GND. If the spectral
frequencies of the internally generated switching noise on the
supply pins cross the series resonant point of an individual bypass
capacitor, its overall impedance begins to look inductive and thus
increases with increasing frequency. The parallel capacitor
combination shown ensures that a low impedance path to ground
exists for frequencies well above the noise bandwidth.
Figure 5. VCC Power Supply Bypass
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
DUT
MC100ES6226
VTT
RT = 50
ZO = 50
VTT
VCC
MC100ES6226
VCC
33...100 nF
0.1 nF
相关PDF资料 |
PDF描述 |
|---|---|
| SY10E160JZ | IC PARITY GEN/CHKER 12BIT 28PLCC |
| ICS8535AG-31LF | IC CLOCK BUFFER MUX 2:4 20-TSSOP |
| ICS8533AG-01LF | IC CLOCK BUFFER MUX 2:4 20-TSSOP |
| VE-26V-MW-F4 | CONVERTER MOD DC/DC 5.8V 100W |
| VE-JNJ-MZ-F1 | CONVERTER MOD DC/DC 36V 25W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100ES6226ACR2 | 功能描述:时钟驱动器及分配 FSL 1-9 Diff LVPECL Clk Div Fanout Buff. RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6226FA | 功能描述:时钟缓冲器 Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100ES6254AC | 功能描述:时钟驱动器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6254ACR2 | 功能描述:时钟驱动器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC100ES6254FA | 功能描述:时钟缓冲器 Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。