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参数资料
| 型号： | MC12430FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 6/12页 |
| 文件大小： | 503K |
| 代理商： | MC12430FA |
MC12430
3
MOTOROLA
PIN DESCRIPTIONS
Pin Name
Function
Inputs
XTAL1, XTAL2
These pins form an oscillator when connected to an external series–resonant crystal.
S_LOAD
(Int. Pulldown)
This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when
this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.
S_DATA
(Int. Pulldown)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK
(Int. Pulldown)
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
P_LOAD
(Int. Pullup)
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when
this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper
operation. P_LOAD is state sensitive.
M[8:0]
(Int. Pullup)
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of
P_LOAD. M[8] is the MSB, M[0] is the LSB.
N[1:0]
(Int. Pullup)
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition
of P_LOAD.
OE
(Int. Pullup)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT
output.
Outputs
FOUT, FOUT
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
TEST
The function of this output is determined by the serial configuration bits T[2:0]. The output is single–ended ECL.
Power
VCC
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V
(VCC = PLL_VCC). Current drain through VCC ≈ 85 mA.
PLL_VCC
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply
is connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC ≈ 15 mA.
GND
These pins are the negative supply for the chip and are normally all connected to ground.
Other
FREF_EXT (Int. Pulldown)
LVCMOS/CMOS input which can be used as the PLL reference.
XTAL_SEL
(Int. Pullup)
LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal.
A HIGH selects the crystal input.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC12430
High Frequency Clock Synthesizer
NETCOM
IDT High Frequency Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC12430
3
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