参数资料
型号: MC13224V
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA99
封装: 9.50 X 9.50 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, LGA-99
文件页数: 43/54页
文件大小: 490K
代理商: MC13224V
MC1322x Technical Data, Rev. 1.3
48
Freescale Semiconductor
8
Developer Environment
The MC1322x family is supported by a full set of hardware/software evaluation and development tools.
8.1
Hardware Development Interfaces
The ARM debug environment supports both a JTAG debug interface and an extended capability Nexus
interface.
8.1.1
JTAG Hardware Debug Port
The JTAG port is the simpler and more common debug port for the ARM core. A standard 20-pin
connector as described in Section 6.2.1, “ARM JTAG Interface Connector””, is connected to the TDI,
TMS, TCK, TDO, and RTCK signals of the MC1322x. Through the JTAG serial interface, standard debug
and development activities such as accessing memory and registers, control of the CPU, download of
FLASH memory, and software debug can be accomplished.
8.1.2
A7S Nexus3 (NEX) ARM7 Core Development Interface
The development and debug environment of the ARM7TDMI-S core is based on the A7S Nexus3 interface
(compliant with a Class 3 device of the IEEE-ISTO 5001 standard for real-time embedded system design).
This interface allows expansion of the development features of the JTAG port (through the addition of
auxiliary signals, see Section 6.2.2, “Nexus Mictor Interface Connector”). Development features include:
Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program
flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool
to interpolate what transpires between the discontinuities. Thus static code may be traced.
Table 23. ADC Timing/Performance Characteristics
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Resolution
-12
Bits
Effective Resolution
8
Bits
Number of input channels
8
ADC conversion clock frequency
fADCCLK
-
300
KHz
Conversion cycles (continuous convert)
CCP
6
ADCCLK
cycles
Conversion time
Tconv
20
-
μs
Input Leakage Current
-
nA
Analog Input Voltage1
1 Analog input must be between V
REFL + 0.2 and VREFH - 0.2 for valid conversion.
VAIN
VDD
VREFL
VREFH
V
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