参数资料
型号: MC13892VKR2
厂商: Freescale Semiconductor
文件页数: 68/158页
文件大小: 0K
描述: IC PMU I.MX51/37/35/27 139MAPBGA
标准包装: 2,000
应用: 电池管理,显示器(LED 驱动器),手持/移动设备,电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 139-TFBGA
供应商设备封装: 139-PBGA(7x7)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Figure 13. Power Gating Diagram
MEMORY HOLD POWER GATING
As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of
the SW4 power domain, to selected circuitry in Low-power modes while cutting off the switcher domain from other peripheral
loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3, are shut down in Memory Hold, so just the
external memory is maintained in self refresh mode.
An external NMOS is to be placed between the direct-connected memory supply and any peripheral loading. The PWGTDRV2
pin controls the gate of the external NMOS and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold
or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.
Figure 14. Memory Hold Circuit
EXITING FROM LOW-POWER OFF MODES
When a Turn On event occurs, any switchers that are active through Low-power Off modes will stay in PFM mode at their
Standby voltage set points until the applicable time slot of the startup sequencer. At that point, the respective switcher is updated
for the PUMSx defined default state for mode and voltage. Subsequent closing of the power gate switches will be coordinated
by software to complete restoration of the full system power tree.
MC13892
Analog Integrated Circuit Device Data
68
Freescale Semiconductor
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