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| 型号： | MC13892VKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 80/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 139MAPBGA |
| 标准包装： | 2,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 139-TFBGA |
| 供应商设备封装： | 139-PBGA（7x7） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
SUPPLIES
stepping. If a switcher runs out of programmable range (in either direction), as constrained by programmable stops, then the
increment or decrement command shall be ignored.
The Switcher Increment / Decrement (SID) function is enabled with SIDEN = 1. This will reassign the function of the DVS1 and
DVS2 pins, from the default toggling between Normal and DVS operating modes, to a jog control mode for the switcher which
DVSx is assigned. Once enabled, the switcher being controlled will start at the Normal mode set point as programmed with
SWx[4:0] and await any jog commands from the processor. The adjustment scheme essentially intercepts the Normal mode set
point SPI bits (i.e., but not DVS or Standby programmed set points), and makes any necessary adjustments based on jog up or
jog down commands. The modified set point bits are then immediately passed to the switching regulator, which would then do a
DVS step in the appropriate direction. The SPI bits containing Normal mode programming are not directly altered.
When configured for SID mode, a high pulse on the DVSx pin will indicate one of 3 actions to take, with the decoding as a
function of how many contiguous SPI clock falling edges are seen while the DVSx pin is held high.
Table 51. SID Control Protocol
Number of SPI CLK Falling
Edges while DVSx = 1
0
1
2
3 or more
Function
No action. Switcher stays at its presently programmed configuration
Jog down. Drive buck regulator output down a single DVS step
Jog up. Drive buck regulator output up a single DVS step
Panic Mode. DVS step the buck regulator output to the Normal mode value as programmed in the SPI register
The SID protocol is illustrated by way of example, assuming SIDEN = 1, and that DVS1 is controlling SW1. SW1 starts out at
its default value of 1.250 V (SW1 = 11010) and is stepped both up and down via the DVS1 pin. The SPI bits SW1 = 11010 do
not change. The set point adjustment takes place in the SID block prior to bit delivery to the switcher's digital control.
SW1 output
Starting Value
1.250
DVS
Up
1.275
DVS
Down
1.250
DVS
Down
1.225
DVS1
Up
Down
Down
SPICLK
1
2
1
1
SPICLK shut down
when not used
Figure 21. SID Control Example for Increment & Decrement
SID Panic Mode is provided for rapid recovery to the programmed Normal mode output voltage, so the processor can quickly
recover to its high performance capability with a minimum of communication latency. In Figure 22 , Panic Mode recovery is
illustrated as an Increment step, initiated by the detection of the second falling SPI clock edge, followed by a continuation to the
programmed SW1[4:0] level (1.250 V in this example), due to the detection of the third contiguous falling edge of SPI clock while
DVS1 is held high.
MC13892
Analog Integrated Circuit Device Data
80
Freescale Semiconductor
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