- 您现在的位置：买卖IC网 > PDF目录16588 > MC13892VKR2 (Freescale Semiconductor)IC PMU I.MX51/37/35/27 139MAPBGA PDF资料下载
参数资料
| 型号： | MC13892VKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 73/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 139MAPBGA |
| 标准包装： | 2,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 139-TFBGA |
| 供应商设备封装： | 139-PBGA（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页当前第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页
FUNCTIONAL DEVICE OPERATION
SUPPLIES
The Buck regulator topology includes an integrated synchronous rectifier, meaning that the rectifying diode is implemented on
the chip as a low ohmic FET. The placement of an external diode is therefore not required, but overall switcher efficiency may
benefit from this. The buck regulators permit a 100% duty cycle operation.
During normal operation, several power modes are possible depending on the loading. For medium and full loading,
synchronous PWM control is the most efficient, while maintaining a constant switching frequency. Two PWM modes are
available: the first mode sacrifices low load efficiency for a continuous switching operation (PWM-NPS). The second mode offers
better low load efficiency by allowing the absence of switching cycles at low output loading (PWM-PS). This pulse skipping
feature improves efficiency by reducing dynamic switching losses by simply switching less often.
In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM)
control scheme. The frequency spectrum in this case will be a function of input and output voltage, loading, and the external
components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes
and Deep Sleep operation.
Buck modes of operation are programmable for explicitly defined or load-dependent control (Adaptive). Refer to the Buck
regulators section in Power Control System for details.
Common control bits available to each buck regulator may be designated with a suffix “x” within this specification, where x
stands for 1, 2, 3, or 4 (i.e., SWx = SW1, SW2, SW3, and SW4).
The output voltages of the buck regulators are SPI configurable, and two output ranges are available, individually programmed
with SWxHI for SW2, SW3, and SW4 bucks, SW1 is limited to only one output range. Presets are available for both the Normal
and Standby operation. SW1 and SW2 also include pin controlled DVS operation. When transitioning from one voltage to
another, the output voltage slope is controlled in steps of 25 mV per time step (time step as defined for DVS stepping for SW1
and SW2, fixed at 4.0 μ s for SW3 and SW4). This allows for support of dynamic voltage scaling (DVS) by using SPI driven voltage
steps, state machine defined modes, and direct DVSx pin control.
When initially activated, switcher outputs will apply controlled stepping to the programmed value. The soft start feature limits
the inrush current at startup. A built-in current limiter ensures that during normal operation, the maximum current through the coil
is not exceeded. This current limiter can be disabled by setting the SWILIMB bit.
Point of Load feedback is intended for minimizing errors due to board level IR drops.
SWITCHING FREQUENCY
The switchers are driven by a high frequency clock. By default, the PLL generates an effective 3.145728 MHz signal based
upon the 32.768 kHz oscillator signal by multiplying it by 96. To reduce spurious radio channels, the PLL can be programmed
Table 44. PLL Multiplication Factor
PLLX[2:0]
000
001
010
011
100 (default)
101
110
111
Multiplication
Factor
84
87
90
93
96
99
102
105
Switching Frequency (Hz)
2 752 512
2 850 816
2 949 120
3 047 424
3 145 728
3 244 032
3 342 336
3 440 640
To reduce overall current drain, the PLL is automatically turned off if all switchers are in a PFM mode or turned off, and if the
PLL clock signal is not needed elsewhere in the system. The clocking system provides nearly instantaneously, a high frequency
clock to the switchers when the switchers are activated or exit the PFM mode for PWM mode. The PLL can be configured for
continuous operation by setting the SPI bit PLLEN = 1.
MC13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
73
相关PDF资料 |
PDF描述 |
|---|---|
| MC13892BJVLR2 | IC PMU I.MX51/37/35/27 186MAPBGA |
| 862546-8 | CONN LEAD ASSY DBL-END 16AWG 24" |
| RCA18DTMN | CONN EDGECARD 36POS R/A .125 SLD |
| AK673-5-R | CABLE USB B-B MALE DBL SHIELD 5M |
| RCA18DTMH | CONN EDGECARD 36POS R/A .125 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC13892VL | 功能描述:PMIC 解决方案 5/28V BCK/BST PMUIC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC13892VLR2 | 功能描述:PMIC 解决方案 5/28V BCK/BST PMUIC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC1-38RX | 制造商:3M Electronic Products Division 功能描述:NON INSL COPPER SEAMLESS RING TE 制造商:3M Electronic Products Division 功能描述:80610253439 制造商:3M Electronic Products Division 功能描述:80610253439 MC1-38RX S/LOK RING TERMINAL |
| MC1391 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:TV HORIZONTAL PROCESSOR |
| MC13917-1900EVK | 功能描述:射频开发工具 MC13917_1900_EVK RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
发布紧急采购，3分钟左右您将得到回复。