参数资料
型号: MC15XS3400CPNAR2
厂商: Freescale Semiconductor
文件页数: 36/52页
文件大小: 0K
描述: IC SWITCH HIGH SIDE QUAD 24-QFN
标准包装: 1,200
类型: 高端开关
输出数: 4
Rds(开): 15 毫欧
内部开关:
电流限制: 5A
输入电压: 6 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-PowerQFN
供应商设备封装: 24-PQFN(12x12)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses (D[14:10]) and their impact on device operation.
default value [00] corresponds to the medium speed slew rate
Table 13. Slew Rate Speed Selection
ADDRESS XX000 — STATUS REGISTER
(STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
SR1_s (D4)
0
0
1
1
SR0_s (D3)
0
1
0
1
Slew Rate Speed
medium (default)
low
high
Not used
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
ADDRESS A 1 A 0 001— OUTPUT PWM CONTROL
REGISTER (PWMR_S )
The PWMR_s register allows the MCU to control the state
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
of the D14 : D13 bits ( Table 12 ).
Table 12. Output Selection
Incoming message bits D2 : D0 reflect the desired output
that will be delayed of predefined PWM clock rising edges
number, as shown Table 8 , page 28 (only available for
PWM_en bit is set to logic [1]).
ADDRESS A 1 A 0 011 — OUTPUT CONFIGURATION
REGISTER (CONFR1_S)
The CONFR1_s register allows the MCU to configure
corresponding output fault management through the SPI.
Each output “s” is independently selected for configuration
based on the state of the D14 : D13 bits ( Table 12 ).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the
autoretry counter for the selected output, the default value [0]
A 1 (D14)
0
0
1
1
A 0 (D13)
0
1
0
1
HS Selection
HS0 (default)
HS1
HS2
HS3
corresponds to enable auto-retry feature without time
limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-
retry for the selected output, the default value [0] corresponds
to enable this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard
A logic [1] on bit D8 (28W_s) selects the 28 W over-
current protection profile: the over-current thresholds are
divided by 2 and, the inrush and cooling responses are
dedicated to 28 W lamp.
Bit D7 sets the output state. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown Table 7 , page 28 .
ADDRESS A 1 A 0 010— OUTPUT CONFIGURATION
REGISTER (CONFR0_S )
The CONFR0_s register allows the MCU to configure
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14 : D13 bits ( Table 12 ).
shorted to VPWR protection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output
open-load detection for the selected output, the default value
[0] corresponds to enable this feature ( Table 14 ).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF
output open-load detection for the selected output, the
default value [0] corresponds to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output
open-load detection for LEDs for the selected output, the
default value [0] corresponds to ON output open-load
detection is set for bulbs ( Table 14 ).
Table 14. ON Open-load Selection
OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
will enable the output for direct control. A logic [1] on bit D5
will disable the output from direct control (in this case, the
output is only controlled by On bit).
0
0
1
0
1
X
enable with bulb threshold
(default)
enable with LED threshold
disable
D4:D3 bits (SR1_s and SR0_s) are used to select the high
or medium or low speed slew rate for the selected output, the
15XS3400
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
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