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参数资料
| 型号： | MC33780EGR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO16 |
| 封装： | 1.27 MM PITCH, ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 19/37页 |
| 文件大小： | 851K |
| 代理商： | MC33780EGR2 |
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Analog Integrated Circuit Device Data
26
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 22. State Diagram of Transmit FIFO
From TX_NOT_EMPTY, several things can happen.
Additional values can be pushed into the FIFO if the push
pointer is the same as the pop pointer minus one. This push
fills the FIFO so the state advances to TX_FULL. Each time
a new data value is pushed into the FIFO, the push pointer is
incriminated. From TX_NOT_EMPTY, values may also be
popped from the FIFO, freeing a stage for additional data. If
the pop pointer is the same as the push pointer minus one,
the pop removes the last value in the FIFO, so
X_FIFO_EMPTY is set to true and the state changes back to
TX_IDLE. Each time a value is popped, the pop pointer is
incremental.
When the transmit FIFO is full, no additional data can be
written into the FIFO, so no new push requests will be
generated. From TX_FULL, the only valid change is caused
by a pop, which causes the pop pointer to increment and the
state goes back to TX_NOT_EMPTY. (Of course reset, abort,
or disable could cause the state to asynchronously change to
the TX_IDLE state.)
Figure 23 describes the operation of the receive FIFO.
State transitions in this state machine occur at the trailing
edges of R_FIFO_PUSH and R_FIFO_POP. The receive
FIFO is four levels deep, including the stage which receives
serial data from the current DBUS transfer and the stage
that is accessible for SPI reads. In order to assure coherence
of data and status, each FIFO stage includes an extra bit for
the CRC error status for each received data word. Also for
coherency, the DBUS transfer state machine imposes a
delay at the end of a DBUS transfer to assure that the CRC
status is stable before issuing the R_FIFO_PUSH request.
The RX_IDLE state is asynchronously entered at system
reset, when the enable bit goes low, or when there is an
abort.
During normal operation of the receive FIFO, values are
pushed into the FIFO from the DBUS serial interface, causing
the push pointer to increment. After the SPI has read a data
word, the receive FIFO is popped, which makes the location
available for additional data from the DBUS interface (it is the
user's responsibility to read status and data within the same
burst to assure coherence). The RX_NOT_EMPTY state is
active as long as there is some data in the FIFO.
The RX_FULL state is entered when enough data has
been pushed into the FIFO from the DBUS interface to cause
the push pointer to catch up to the pop pointer. Since it is not
possible to introduce another DBUS serial character without
reading (pop) the receive FIFO, it is not possible to overflow
the receive FIFO.
TX_IDLE
TX_NOT_EMPTY
TX_FULL
~EN or ABORT or RSTB ACTIVE/
X_PUSH_PTR = 0;
X_POP_PTR = 0;
X_FIFO_EMPTY = TRUE;
X_FIFO_POP & X_POP_PTR = X_PUSH_PTR-1/
X_POP_PTR = X_POP_PTR+1;
X_FIFO_EMPTY = TRUE;
X_FIFO_POP & X_POP_PTR != X_PUSH_PTR-1/
X_POP_PTR = X_POP_PTR+1;
X_FIFO_POP/
X_FIFO_POP = X_FIFO_POP+1;
X_FIFO_PUSH & X_PUSH_PTR = X_POP_PTR-1/
X_PUSH_PTR = X_PUSH_PTR+1;
X_FIFO_PUSH & X_PUSHPTR != X_POP_PTR-1
X_PUSH_PTR = X_PUSH_PTR+1;
X_FIFO_PUSH/
X_PUSH_PTR = X_PUSH_PTR+1;
X_FIFO_EMPTY = FALSE;
STATE TRANSISTIONS OCCUR
ON NEG EDGES OF X_FIFO_PUSH
AND X_FIFO_POP
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