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参数资料
型号： MC33889DPEGR2
厂商： Freescale Semiconductor
文件页数： 13/59页
文件大小： 0K
描述： IC SYSTEM BASE W/CAN 28SOIC
标准包装： 1,000
系列： *
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
33889
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Loop time Tx to Rx, no bus failure, MC33889D only ((27),
Figure 6) (ISO ICT test series 10)
Tx high to low transition (dominant edge)
Tx low to high transition (recessive edge)
tLOOPRD
-
1.15
1.45
1.5
s
Loop time Tx to Rx, with bus failure, MC33889D only ((27),
Figure 7) (ISO ICT test series 10)
Tx high to low transition (dominant edge)
Tx low to high transition (recessive edge)
tLOOPRD-F
-
1.9
s
Loop time Tx to Rx, with bus failure and
1.5 V gnd shift, 5
nodes network, MC33889D,((28), Figure 8, ISO ICT tests
series 11)
tLOOPRD/DR-F+GS
3.6
s
Min. Dominant Time For Wake-up On CANL or CANH
(Term VBAT; VSUP = 12 V) Guaranteed by design.
MC33889B
MC33889D
tWAKE
-
8.0
30
16
-
30
s
Failure 3 Detection Time (Normal Mode)
tDF3
10
30
80
s
Failure 3 Recovery Time (Normal Mode)
tDR3
-
160
-
s
Failure 6 Detection Time (Normal Mode)
tDF6
50
200
500
s
Failure 6 Recovery Time (Normal Mode)
tDR6
150
200
1000
s
Failure 4, 7 Detection Time (Normal Mode)
tDF47
0.75
1.5
4.0
ms
Failure 4, 7 Recovery Time (Normal Mode)
tDR47
10
30
60
s
Failure 3a, 8 Detection Time (Normal Mode)
tDF8
0.75
1.7
4.0
ms
Failure 3a, 8 Recovery Time (Normal Mode)
tTDR8
0.75
1.5
4.0
ms
Failure 4, 7 Detection Time, (Term VBAT; VSUP = 12 V)
tDR47
0.8
1.2
8.0
ms
Failure 4, 7 Recovery Time (Term VBAT; VSUP = 12 V)
tDR47
-
1.92
-
ms
Failure 3 Detection Time (Term VBAT; VSUP = 12 V)
tDR3
-
3.84
-
ms
Failure 3 Recovery Time (Term VBAT; VSUP = 12 V)
tDR3
-
1.92
-
ms
Failure 3a, 8Detection Time (Term VBAT; VSUP = 12 V)
tDR8
-
2.3
-
ms
Failure 3a, 8 Recovery Time (Term VBAT; VSUP = 12 V)
tDR8
-
1.2
-
ms
Edge Count Difference Between CANH and CANL for Failures 1,
2, 5 Detection (Failure bit set, Normal Mode)
ECDF
-
3
-
Edge Count Difference Between CANH And CANL For Failures
1, 2, 5 Recovery (Normal Mode)
ECDR
-
3
-
TX Permanent Dominant Timer Disable Time
(Normal Mode And Failure Mode)
tTX,D
0.75
-
4.0
ms
TX Permanent Dominant Timer Enable Time
(Normal Mode And Failure Mode)
tTX,E
10
-
60
s
Notes
27.
AC characteristic according to ISO11898-3, tested per figure 5 and 6. Guaranteed by design, room temperature only.
28.
AC characteristic according to ISO11898-3, tested per figure 7. Max reported is the typical measurement under the worst condition (gnd
shift, dominant/recessive edge, at source or destination node. ref to ISO test specification). Guaranteed by design, room temperature
only.
Table 5. Dynamic Electrical Characteristics (continued)
VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40 to 150 °C, unless otherwise noted. Typical values noted
reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Conditions
Symbol
Min
Typ
Max
Unit
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