参数资料
型号: MC33912BAC
厂商: Freescale Semiconductor
文件页数: 46/95页
文件大小: 0K
描述: IC SYSTEM BASIS CHIP 32LQFP
标准包装: 250
应用: 系统基础芯片
电流 - 电源: 4.5mA
电源电压: 5.5 V ~ 27 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
MC33912G5AC / MC34912G5AC
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Interrupt Mask Register - IMR
This register allows masking of some of the interrupt sources.
No interrupt will be generated to the MCU and no flag will be
set in the ISR register. The 5.0 V Regulator over-temperature
prewarning interrupt and under-voltage (VSUV) interrupts
can not be masked and will always cause an interrupt.
Writing to the IMR will return the ISR.
Table 30. Interrupt Mask Register - $E
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V SUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
C3
C2
C1
C0
Interrupt Source Register - ISR
Write
Reset
Value
HSM
1
LSM
1
LINM
1
VMM
1
This register allows the MCU to determine the source of the
last interrupt or wake-up respectively. A read of the register
acknowledges the interrupt and leads IRQ pin to high, in case
Reset
Condition
POR
there are no other pending interrupts. If there are pending
interrupts, IRQ will be driven high for 10 μs and then be
driven low again.
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
Table 31. Interrupt Source Register - $E/$F
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
S3
S2
S1
S0
LSM - Low Side Interrupt Mask
Read
ISR3
ISR2
ISR1
ISR0
This write-only bit enables/disables interrupts generated in
the low side block.
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
Table 32. Interrupt Sources
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
Table 32 . If no interrupt is pending then all bits are 0.
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
no interrupt
Lx Wake-up from Stop and Sleep mode
-
-
LIN Wake-up
Voltage Monitor Interrupt
no interrupt
-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
LIN Interrupt (RXSHORT, TXDOM, LIN OT)
Voltage Monitor Interrupt
none
highest
(Low Voltage and VDD over-temperature)
(High Voltage)
0
1
1
0
Forced Wake-up
-
lowest
33912
Analog Integrated Circuit Device Data ?
46
Freescale Semiconductor
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