参数资料
型号: MC56F8006VWL
厂商: Freescale Semiconductor
文件页数: 26/106页
文件大小: 0K
描述: DSC 16K FLASH 32MHZ 28-SOIC
标准包装: 26
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,LIN,SCI,SPI
外围设备: LVD,POR,PWM,WDT
输入/输出数: 23
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 15x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 734 (CN2011-ZH PDF)
配用: MC56F8006DEMO-ND - DEMO BOARD FOR MC56F8006
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Signal/Connection Descriptions
Freescale Semiconductor
26
TDI
(GPIOD0)
(ANB12)
(SS)
(TIN2)
(CMP0_
OUT)
23
30
26
45
Input
Input/
Output
Analog
Input
Output
Input,
internal
pullup
enabled
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB12 — Analog input to channel 12 of ADCB
SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
TIN2 — Dual timer module channel 2 input.
CMP1_OUT — Analog comparator 1 output.
After reset, the default state is TDI.
TDO
(GPIOD1)
(ANB10)
(T0)
(CMP2_
OUT)
25
32
28
48
Output
Input/
Output
Analog
Input
Input/
Output
Output,
tri-stated,
internal
pullup
enabled
Test Data Output — This three-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANB10 — Analog input to channel 10 of ADCB.
T0 — Dual timer module channel 0 input/output.
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TDO.
TCK
(GPIOD2)
(ANA4 and
CMP1_P2)
(CMP2_
OUT)
9
14
10
22
Input
Input/
Output
Analog
Input
Output
Input,
internal
pullup
enabled
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
ANA4 and CMP1_P2 — Analog input to channel 4 of ADCA and
positive input 2 of analog comparator 1.
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TCK.
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
Signal
Name
28
SOIC
32
LQFP
32
PSDI
P
48
LQFP
Type
State
During
Reset
Signal Description
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