参数资料
型号: MC56F8006VWL
厂商: Freescale Semiconductor
文件页数: 66/106页
文件大小: 0K
描述: DSC 16K FLASH 32MHZ 28-SOIC
标准包装: 26
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,LIN,SCI,SPI
外围设备: LVD,POR,PWM,WDT
输入/输出数: 23
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 15x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 734 (CN2011-ZH PDF)
配用: MC56F8006DEMO-ND - DEMO BOARD FOR MC56F8006
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
62
Figure 31. RXD Pulse Width
Figure 32. TXD Pulse Width
8.13.3
Inter-Integrated Circuit Interface (I2C) Timing
Table 31. I2C Timing
Characteristic
Symbol
Standard Mode
Unit
Minimum
Maximum
SCL Clock Frequency
fSCL
0100
MHz
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
tHD; STA
4.0
s
LOW period of the SCL clock
tLOW
4.7
s
HIGH period of the SCL clock
tHIGH
4.0
s
Set-up time for a repeated START condition
tSU; STA
4.7
s
Data hold time for I2C bus devices
tHD; DAT
01
1 The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.452
2 The maximum t
HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
s
Data set-up time
tSU; DAT
250
ns
Rise time of SDA and SCL signals
tr
1000
ns
Fall time of SDA and SCL signals
tf
—300
ns
Set-up time for STOP condition
tSU; STO
4.0
s
Bus free time between STOP and START condition
tBUF
4.7
s
Pulse width of spikes that must be suppressed by the input filter
tSP
N/A
ns
RXDPW
RXD
SCI receive
data pin
(Input)
TXDPW
TXD
SCI receive
data pin
(Input)
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