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参数资料
| 型号： | MC56F8011VFAE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 106/125页 |
| 文件大小： | 1702K |
| 代理商： | MC56F8011VFAE |
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Resets
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
81
All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency1,
which is the same as the main processor frequency in this architecture. The COP timer runs at
MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is
the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using
TCR and PCR controls, provided the PLL is active and selected.
6.6 Resets
The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the
external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,
which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP
reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The
first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On
Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column
provides additional detail.
Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks
use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this
phase of reset.
1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.
Table 6-4 Primary System Resets
Reset Sources
Reset Signal
POR
External
Software
COP
Comments
EXTENDED_POR
X
Stretched version of POR. Relevant 64
Relaxation Oscillator Clock cycles after
POR deasserts.
CLKGEN_RST
X
Released 32 Relaxation Oscillator Clock
cycles after all reset sources have
released.
PERIP_RST
X
Releases 32 Relaxation Oscillator Clock
cycles after the CLKGEN_RST is
released.
CORE_RST
X
Releases 32 SYS_CLK periods after
PERIP_RST is released.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC56F8013 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013MFAE | 功能描述:数字信号处理器和控制器 - DSP, DSC 16Bit DSPHC ANGUILLA RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MC56F8013MFAER2 | 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC ANGUILLA - Tape and Reel |
| MC56F8013PB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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