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参数资料
| 型号： | MC56F8011VFAE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 110/125页 |
| 文件大小： | 1702K |
| 代理商： | MC56F8011VFAE |
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Flash Security Enabling
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
85
7.1 Flash Security Enabling
After the user has programmed the Flash with the application code, the 56F8013/56F8011 can be secured
by programming the security words located in the FM configuration field, which are located at the last nine
words of Program Flash. These non-volatile words will keep the part secured through reset and through
power-down of the device. To enable the flash security, program $E70A into program memory location
$1FF7. No other data programs in this location can secure the flash. Refer to the Flash Memory chapter in
the 56F801X Peripheral User Manual for more detail. When Flash security mode is enabled, the
56F8013/56F8011 will disable the core EOnCE debug capabilities. Normal program execution is
otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
The 56F8013/56F8011 have several operating functional and debug modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be read without
explicit user permission.
7.2.1
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the 56F8013/56F8011 boot, the chip-level JTAG TAP (Test
Access Port) is active and provides the chip’s boundary scan capability and access to the ID register, but
proper implementation of Flash security will block any attempt to access the internal Flash memory via
the EOnCE port when security is enabled.
7.2.2
Flash Lockout Recovery Using JTAG
If a user inadvertently enables security on the 56F8013/56F8011, the only lockout recovery mechanism is
the complete erasure of the internal Flash contents, including the configuration field, and thus disables
security (the protection register is cleared). This does not compromise security, as the entire contents of
the user’s secured code stored in Flash are erased before security is disabled on the 56F8013/56F8011 on
the next reset or power-up sequence.
To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must
first
be
shifted
into
the
chip-level
TAP
controller’s
instruction
register.
Once
the
LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value
must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user
must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence.
The controller must remain in this state until the erase sequence has completed. Refer to the 56F801X
Peripheral User Manual for more details, or contact Freescale.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by advancing the TAP state machine to the reset state) and the 56F8013/56F8011 (by asserting
external chip reset) to return to normal unsecured operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC56F8013 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013MFAE | 功能描述:数字信号处理器和控制器 - DSP, DSC 16Bit DSPHC ANGUILLA RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MC56F8013MFAER2 | 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC ANGUILLA - Tape and Reel |
| MC56F8013PB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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