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参数资料
型号： MC56F8013MFAE
厂商： Freescale Semiconductor
文件页数： 107/126页
文件大小： 0K
描述： IC DIGITAL SIGNAL CTLR 32-LQFP
标准包装： 1,250
系列： 56F8xxx
核心处理器： 56800E
芯体尺寸： 16-位
速度： 32MHz
连通性： I²C，SCI，SPI
外围设备： POR，PWM，WDT
输入/输出数： 26
程序存储器容量： 16KB（8K x 16）
程序存储器类型： 闪存
RAM 容量： 2K x 16
电压 - 电源 (Vcc/Vdd)： 3 V ~ 3.6 V
数据转换器： A/D 6x12b
振荡器型： 内部
工作温度： -40°C ~ 125°C
封装/外壳： 32-LQFP
包装： 托盘
Resets
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
81
All peripherals, except the COP/watchdog timer, run at the system clock (peripheral bus) frequency1,
which is the same as the main processor frequency in this architecture. The COP timer runs at
MSTR_OSC / 1024. The maximum frequency of operation is SYS_CLK = 32MHz. The only exception is
the Quad Timer and PWM, which can be configured to operate at three times the system bus rate using
TCR and PCR controls, provided the PLL is active and selected.
6.6 Resets
The SIM supports four sources of reset, as shown in Figure 6-15. The two asynchronous sources are the
external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset,
which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, and the COP
reset. The SIM uses these to generate resets for the internal logic. These are outlined in Table 6-4. The
first column lists the four primary resets which are calculated. The JTAG circuitry is reset by the Power-On
Reset. Columns two through five indicate which reset sources trigger these reset signals. The last column
provides additional detail.
Figure 6-15 provides a graphic illustration of the details in Table 6-4. Note that the POR_Delay blocks
use the Relaxation Oscillator Clock as their time base since other system clocks are inactive during this
phase of reset.
1. The Quad Timer and PWM modules can be operated at three times the IPBus clock frequency.
Table 6-4 Primary System Resets
Reset Sources
Reset Signal
POR
External
Software
COP
Comments
EXTENDED_POR
X
Stretched version of POR. Relevant 64
Relaxation Oscillator Clock cycles after
POR deasserts.
CLKGEN_RST
X
Released 32 Relaxation Oscillator Clock
cycles after all reset sources have
released.
PERIP_RST
X
Releases 32 Relaxation Oscillator Clock
cycles after the CLKGEN_RST is
released.
CORE_RST
X
Releases 32 SYS_CLK periods after
PERIP_RST is released.
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