参数资料
型号: MC56F8013MFAE
厂商: Freescale Semiconductor
文件页数: 112/126页
文件大小: 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
标准包装: 1,250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 26
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 2K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 32-LQFP
包装: 托盘
56F8013/56F8011 Data Sheet, Rev. 12
86
Freescale Semiconductor
7.2.4
Flash Lockout Recovery Without Mass Erase
The user can un-secure a secured device by programming the word $0000 into program memory location
$00 1FF7. After completing the programming, both the JTAG TAP controller and the device must be
reset in order to return to normal unsecured operation. Power-on reset will also reset both.
The user is responsible for directing the device to invoke the flash programming subroutine to reprogram
the word $0000 into program memory location $00 1FF7. This is done by, for example, toggling a specific
pin, or by downloading a user-defined key through serial interfaces.
Note:
Flash contents can only be programmed for 1s to 0s.
7.3 Product Analysis
The recommended method of unsecuring a secured device for product analysis of field failures is via the
method suggested in Section 7.2.4. The customer would need to supply Technical Support with the details
of the protocol to access the subroutines in flash. An alternative method for performing analysis on a
secured device would be to mass-erase and reprogram the flash with the original code, but also either
modify the security word or else not program the security word.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F801X Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F801X Peripheral User Manual.
8.2 Configuration
There are four GPIO ports defined on the 56F8013/56F8011. The width of each port, the associated
peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown
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