参数资料
型号: MC56F8122VFAE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 80 MHz, OTHER DSP, PQFP48
封装: ROHS COMPLIANT, LQFP-48
文件页数: 54/136页
文件大小: 719K
代理商: MC56F8122VFAE
56F8322 Techncial Data, Rev. 16
24
Freescale Semiconductor
Preliminary
PWMA1
(GPIOA1)
4Schmitt
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA1 — This is one of six PWMA output pins.
Port A GPIO - This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA1.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PWMA2
(SS1)
(GPIOA2)
6
Output
Schmitt
Input
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA2 — This is one of six PWMA output pins.
SPI 1 Slave Select — SS1 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA2.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PWMA3
(MISO1)
(GPIOA3)
7
Output
Schmitt
Input/
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA3 — This is one of six PWMA output pins.
SPI 1 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA3.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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