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| 型号： | MC56F8122VFAE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 80 MHz, OTHER DSP, PQFP48 |
| 封装： | ROHS COMPLIANT, LQFP-48 |
| 文件页数： | 87/136页 |
| 文件大小： | 719K |
| 代理商： | MC56F8122VFAE |
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56F8322 Techncial Data, Rev. 16
54
Freescale Semiconductor
Preliminary
4.8 Factory-Programmed Memory
The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader
program. The Serial Bootloader application can be used to load a user application into the Program and
Data Flash (not available on the 56F8122) memories of the device. The 56F83xx SCI/CAN Bootloader
User Manual provides detailed information on this firmware. An application note, Production Flash
Programming, details how the Serial Bootloader program can be used to perform production Flash
programming of the on-board Flash memories as well as other optional methods.
Like all the Flash memory blocks, the Boot Flash can be erased and programmed by the user. The Serial
Bootloader application is programmed as an aid to the end user, but is not required to be used or maintained
in the Boot Flash memory.
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
For further information, see Table 4-3, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
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相关代理商/技术参数 |
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| MC56F8123 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:16-bit Hybrid Controllers |
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| MC56F8123VFBE | 功能描述:数字信号处理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MC56F8135 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller |
| MC56F8135E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controller |
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