参数资料
型号: MC56F8122VFAE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 80 MHz, OTHER DSP, PQFP48
封装: ROHS COMPLIANT, LQFP-48
文件页数: 93/136页
文件大小: 719K
代理商: MC56F8122VFAE
56F8322 Techncial Data, Rev. 16
6
Freescale Semiconductor
Preliminary
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 7
1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 7
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 9
1.3. Award-Winning Development Environment 10
1.4. Architecture Block Diagram . . . . . . . . . . . . . 11
1.5. Product Documentation . . . . . . . . . . . . . . . 15
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 15
Part 2: Signal/Connection Descriptions . . 16
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part 3: On-Chip Clock Synthesis (OCCS) . 28
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2. External Clock Operation . . . . . . . . . . . . . . 28
3.3. Use of On-Chip Relaxation Oscillator . . . . . 30
3.4. Internal Clock Operation . . . . . . . . . . . . . . . 30
3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part 4: Memory Map . . . . . . . . . . . . . . . . . . 32
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 33
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 36
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 38
4.7. Peripheral Memory Mapped Registers . . . . 38
4.8. Factory-Programmed Memory . . . . . . . . . . 54
Part 5: Interrupt Controller (ITCN) . . . . . . . 54
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3. Functional Description . . . . . . . . . . . . . . . . 54
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 56
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 56
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 57
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Part 6: System Integration Module (SIM) . . 79
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . 80
6.4. Operating Mode Register. . . . . . . . . . . . . . . 81
6.5. Register Descriptions. . . . . . . . . . . . . . . . . . 81
6.6. Clock Generation Overview . . . . . . . . . . . . . 93
6.7. Power-Down Modes. . . . . . . . . . . . . . . . . . . 93
6.8. Stop and Wait Mode Disable Function . . . . 94
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Part 7: Security Features . . . . . . . . . . . . . . 95
7.1. Operation with Security Enabled . . . . . . . . . 95
7.2. Flash Access Blocking Mechanisms . . . . . . 95
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 98
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . .100
Part 9: Joint Test Action Group (JTAG) . . 100
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 100
Part 10: Specifications . . . . . . . . . . . . . . . . 101
10.1. General Characteristics . . . . . . . . . . . . . .101
10.2. DC Electrical Characteristics . . . . . . . . . .105
10.3. AC Electrical Characteristics . . . . . . . . . .109
10.4. Flash Memory Characteristics . . . . . . . . . 110
10.5. External Clock Operation Timing . . . . . . .111
10.6. Phase Locked Loop Timing . . . . . . . . . . . 111
10.7. Oscillator Parameters . . . . . . . . . . . . . . . 112
10.8. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . . . . 113
10.9. Serial Peripheral Interface (SPI) Timing . .115
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .118
10.11. Quadrature Decoder Timing . . . . . . . . . .118
10.12. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . .119
10.13. Controller Area Network (CAN) Timing .120
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . .120
10.15. Analog-to-Digital Converter
(ADC) Parameters . . . . . . . . . . . .121
10.16. Equivalent Circuit for ADC Inputs . . . . . .124
10.17. Power Consumption . . . . . . . . . . . . . . . 124
Part 11: Packaging . . . . . . . . . . . . . . . . . . 126
11.1. 56F8322 Package and
Pin-Out Information . . . . . . . . . . .126
11.2. 56F8122 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . 128
Part 12: Design Considerations . . . . . . . . 131
12.1. Thermal Design Considerations . . . . . . . 131
12.2. Electrical Design Considerations . . . . . . .132
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .133
Part 13: Ordering Information . . . . . . . . . 134
Table of Contents
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