Electrical and Thermal Characteristics
12-6
M68060 USER’S MANUAL
MOTOROLA
12.7 INPUT AC TIMING SPECIFICATIONS (VCC = 3.3 VDC ± 5%)
NOTES:
1. BCLK is not a pin signal name. It is a virtual bus clock derived from the combination of CLK and CLKEN. A BCLK
rising edge coincides with a CLK in which CLKEN is asserted. A BCLK falling edge is insignificant. When a reference
to BCLK is used to describe input timing, it means that the specific input is recognized only on rising CLK edges in
which CLKEN is asserted. A timing reference to CLK means that the input is recognized at any rising CLK edge, in-
cluding those edges in which CLKEN is negated.
2. 40 MHz available only for the MC68EC060.
Num
Characteristic
40 MHz2
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min.
Max.
15
Data-In Valid to BCLK (Setup)
3
—
2
—
1
—
ns
16
BCLK to Data-In Invalid (Hold)
2
—
2
—
2
—
ns
17
BCLK to Data-In High Impedance
(Read Followed by Write)
—
7
—
7
—
7
ns
22a TA, Valid to BCLK (Setup)
12
—
10
—
7
—
ns
22b TEA Valid to BCLK (Setup)
12
—
10
—
7
—
ns
22c TCI Valid to BCLK (Setup)
12
—
10
—
7
—
ns
22d TBI Valid to BCLK (Setup)
12
—
10
—
7
—
ns
22e TRA Valid to BCLK (Setup)
12
—
10
—
7
—
ns
23
BCLK to TA, TEA, TCI, TBI, TRA Invalid
(Hold)
2
—
2
—
2
—
ns
24
AVEC Valid to BCLK (Setup)
12
—
10
—
7
—
ns
25
BCLK to AVEC Invalid (Hold)
2
—
2
—
2
—
ns
41a BB Valid to BCLK (Setup)
12
—
10
—
7
—
ns
41b BG Valid to BCLK (Setup)
12
—
10
—
7
—
ns
41c CDIS, MDIS Valid to BCLK (Setup)
12
—
10
—
7
—
ns
41d IPL
≈ Valid to CLK (Setup)
3
—
2
—
1
—
ns
41e BTT Valid to BCLK (Setup)
12
—
10
—
7
—
ns
41f
BGR Valid to BCLK (Setup)
12
—
10
—
7
—
ns
42a BCLK to BB Invalid (Hold)
2
—
2
—
2
—
ns
42b BCLK to BG Invalid (Hold)
2
—
2
—
2
—
ns
42c BCLK to CDIS, MDIS Invalid (Hold)
2
—
2
—
2
—
ns
42d CLK to IPLx Invalid (Hold)
2
—
2
—
2
—
ns
42e BCLK to BTT Invalid (Hold)
2
—
2
—
2
—
ns
42f
BCLK to BGR Invalid (Hold)
2
—
2
—
2
—
ns
44a Address Valid to BCLK (Setup)
3
—
2
—
1
—
ns
44c TT1 Valid to BCLK (Setup)
12
—
10
—
7
—
ns
44e SNOOP Valid to BCLK (Setup)
12
—
10
—
7
—
ns
45a BCLK to Address Invalid (Hold)
2
—
2
—
2
—
ns
45c BCLK to TT1 Invalid (Hold)
2
—
2
—
2
—
ns
45e BCLK to SNOOP Invalid (Hold)
2
—
2
—
2
—
ns
46
TS Valid to BCLK (Setup)
12
—
10
—
7
—
ns
47
BCLK to TS Invalid (Hold)
2
—
2
—
2
—
ns
49
BCLK to BB in High Impedance
(MC68060 Assumes Bus Mastership)
—
3
—
3
—
3
ns
51
RSTI Valid to BCLK
3
—
2
—
1
—
ns
52
BCLK to RSTI Invalid (hold)
2
—
2
—
2
—
ns
53
Mode Select Setup to BCLK (RSTI Asserted)
12
—
10
—
7
—
ns
54
BCLK to Mode Selects Invalid (RSTI Assert-
ed)
2
—
2
—
2
—
ns
64
CLA Valid to BCLK (Setup)
12
—
10
—
7
—
ns
65
BCLK to CLA Invalid (Hold)
2
—
2
—
2
—
ns