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| 型号： | MC68334GCFC20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
| 封装： | PLASTIC, QFP-132 |
| 文件页数： | 14/76页 |
| 文件大小： | 444K |
| 代理商： | MC68334GCFC20 |
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MC68334
MOTOROLA
MC68334TS/D REV. 1
21
Figure 8 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time is affected by the
filter time constant and by the amount of difference between the two comparator inputs. Whenever com-
parator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in SYNCR.
During power-up, the MCU does not come out of reset state until the synthesizer locks. Crystal type,
characteristic frequency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, control register SYNCR determines operating frequency and vari-
ous modes of operation. The SYNCR W bit controls a three-bit prescaler in the feedback divider. Setting
W increases VCO speed by a factor of four. The SYNCR Y field determines the count modulus for a
modulo 64 down counter, causing it to divide by a value of Y
+ 1. When W or Y values change, VCO
frequency changes, and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit
that is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is enabled, and system
clock frequency is one-fourth VCO frequency; setting X disables the divider, doubling clock speed with-
out changing VCO speed. There is no relock delay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by the W, X, and Y bits
must be within the limits specified for the MCU. Do not use a combination of bit values that selects either
an operating frequency or a VCO frequency greater than the maximum specified values.
3.3.3 External Bus Clock
The state of the external clock division bit (EDIV) in SYNCR determines clock rate for the external bus
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripher-
als. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency
divided by sixteen. The clock is enabled by the CS10 field in chip select pin assignment register 1
(CSPAR1). ECLK operation during low-power stop is described in the following paragraph. Refer to 3.5
Chip Selects for more information about the external bus clock.
16/32 XFC CONN
1. MAINTAIN LOW LEAKAGE ON THE XFC NODE.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW-FREQUENCY NOISE.
0.01
F
0.1
F
NORMAL OPERATING
ENVIRONMENT
HIGH-STABILITY OPERATING
ENVIRONMENT
C4
C1
VSSI
VDDSYN
XFC1
0.1
F
C3
0.01
F
0.1
F
C4
C1
VSSI
VDDSYN
XFC1, 2
0.1
F
C3
0.01
F
C2
18k
R1
F
SYSTEM
F
REFERENCE 4Y
1
+
() 2
2W
X
+
()
[]
=
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