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| 型号： | MC68334GCFC20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
| 封装： | PLASTIC, QFP-132 |
| 文件页数： | 18/76页 |
| 文件大小： | 444K |
| 代理商： | MC68334GCFC20 |
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MC68334
MOTOROLA
MC68334TS/D REV. 1
25
3.4.2 Function Codes
The CPU32 automatically generates function code signals FC[2:0]. The function codes can be consid-
ered address extensions that automatically select one of eight address spaces to which an address ap-
plies. These spaces are designated as either user or supervisor, and program or data spaces. Address
space seven is designated CPU space. CPU space is used for control information not normally associ-
ated with read or write bus cycles. Function codes are valid while AS is asserted.
3.4.3 Address Bus
Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted.
3.4.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.4.5 Data Bus
Data bus signals DATA[15:0] make up a bidirectional, nonmultiplexed parallel bus that transfers data to
or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During a
read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For a
write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MCU
places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.4.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.4.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1
and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.
During a write cycle, the signals indicate that an external device has successfully stored data and that
the cycle can end. These signals also indicate to the MCU the size of the port for the bus cycle just com-
pleted. (Refer to 3.4.9 Dynamic Bus Sizing).
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT
are asserted simultaneously, the CPU takes a bus error exception.
Table 10 CPU32 Address Space Encoding
FC2
FC1
FC0
Address Space
0
Reserved
0
1
User Data Space
0
1
0
User Program Space
0
1
Reserved
1
0
Reserved
1
0
1
Supervisor Data Space
1
0
Supervisor Program Space
1
CPU Space
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