MOTOROLA
MC68349 USER'S MANUAL
3- 57
State changes occur on the next rising edge of the clock after the internal signal is valid.
The BG signal transitions on the falling edge of the clock after a state is reached during
which G changes. The bus control signals (controlled by T) are driven by the MC68349
immediately following a state change, when bus mastership is returned to the MC68349.
State 0, in which G and T are both negated, is the state of the bus arbiter while the
MC68349 is bus master. R and A keep the arbiter in state 0 as long as they are both
negated.
The MC68349 does not allow arbitration of the external bus during the RMC sequence.
For the duration of this sequence, the MC68349 ignores the BR input. If mastership of the
bus is required during an RMC operation, BERR must be used to abort the RMC
sequence.
3.6.5 Show Cycles
The MC68349 can perform data transfers with its internal modules without using the
external bus, but, when debugging, it is desirable to have address and data information
appear on the external bus. These external bus cycles, called show cycles, are
distinguished by the fact that AS is not asserted externally. DS is used to signal address
strobe timing in show cycles.
After reset, show cycles are disabled and must be enabled by writing to the SHENx bits in
the module configuration register (see Section 4 System Integration Module). When
show cycles are disabled, the A31–A0, FCx, SIZx, and R/W signals continue to reflect
internal bus activity. However, AS and DS are not asserted externally, and the external
data bus remains in a high-impedance state. When show cycles are enabled, DS indicates
address strobe timing and the external data bus contains data. The following paragraphs
are a state-by-state description of show cycles, and Figure 3-38 illustrates a show cycle
timing diagram. Refer to Section 11 Electrical Characteristics for specific timing
information.