5- 10
MC68349 USER’S MANUAL
MOTOROLA
5.2.1.2 SRAM MODE
. Each of the four blocks in the CIC can be used as a 512-byte
SRAM bank accessible only by the CPU32+, as shown in Figure 5-6. Each SRAM bank is
relocatable on any 512-byte boundary. The memory contents can be write-protected on a
bank basis by setting the corresponding write-protect (LWP) bit in the module
configuration register (refer to 5.2.2 Programmer's Model for more information).
512-BYTES
RAM
MEMORY SPACE
32 BITS
BANK LWP BIT
MCR
Figure 5-6. CIC SRAM Block Diagram
CIC SRAM banks are allowed to overlap external memory blocks defined by the SIM49
integrated chip selects and external address decode. An access which hits in the SRAM
bank preempts an external bus cycle. However, all SRAM banks internal to the MC68349,
whether in the CIC or the QDMM, should be mapped to unique memory locations relative
to each other; data values returned for overlapping ranges are undefined. For more
information about the QDMM, see Section 6 Quad Data Memory Module.
5.2.2 Programmer's Model
Figure 5-7 is a programmer's model (register map) of all registers in the CIC. The ADDR
(address) column indicates the offset of the register from the address stored in the SIM49
module base address register (MBAR). The FC (function code) column indicates whether
a register is restricted to supervisor access (S) or available to either supervisor or user
space (S/U) accesses. All registers within the CIC are supervisor-only.
In the registers discussed in the following pages, the number in the upper right hand
corner indicates the offset of the register from the address stored in the module base
address register (MBAR). The numbers on the top line of the register represent the bit
position in the register. The second line contains the mnemonic for the bit. The numbers
below the register represent the bit values after reset. The access privilege is indicated in
the lower right-hand corner.